From 5db9fa7433163139e23465433eb2c1e469439540 Mon Sep 17 00:00:00 2001
From: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Date: Mon, 27 Sep 2021 13:49:15 +0800
Subject: [PATCH] soc/mediatek/mt8186: Initialize watchdog

MT8186 requires writing speical value to mode register to clear
status register. The flow of clear status is different from other
platforms, so we override mtk_wdt_clr_status() for MT8186.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I290b69573a8e58db76814e16b5c17c23413f1108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58835
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8186/Kconfig      |  1 +
 src/soc/mediatek/mt8186/Makefile.inc |  4 ++++
 src/soc/mediatek/mt8186/bootblock.c  |  2 ++
 src/soc/mediatek/mt8186/wdt.c        | 17 +++++++++++++++++
 4 files changed, 24 insertions(+)
 create mode 100644 src/soc/mediatek/mt8186/wdt.c

diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig
index 28589e3bf7..9fa391aca7 100644
--- a/src/soc/mediatek/mt8186/Kconfig
+++ b/src/soc/mediatek/mt8186/Kconfig
@@ -6,6 +6,7 @@ config SOC_MEDIATEK_MT8186
 	select ARCH_ROMSTAGE_ARMV8_64
 	select ARCH_RAMSTAGE_ARMV8_64
 	select HAVE_UART_SPECIAL
+	select SOC_MEDIATEK_COMMON
 
 if SOC_MEDIATEK_MT8186
 
diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc
index c9cb305842..72d67cc007 100644
--- a/src/soc/mediatek/mt8186/Makefile.inc
+++ b/src/soc/mediatek/mt8186/Makefile.inc
@@ -5,22 +5,26 @@ bootblock-y += ../common/mmu_operations.c
 bootblock-$(CONFIG_SPI_FLASH) += spi.c
 bootblock-y += ../common/timer.c
 bootblock-y += ../common/uart.c
+bootblock-y += ../common/wdt.c wdt.c
 
 verstage-$(CONFIG_SPI_FLASH) += spi.c
 verstage-y += ../common/timer.c
 verstage-y += ../common/uart.c
+verstage-y += ../common/wdt.c wdt.c
 
 romstage-y += ../common/cbmem.c
 romstage-y += emi.c
 romstage-$(CONFIG_SPI_FLASH) += spi.c
 romstage-y += ../common/timer.c
 romstage-y += ../common/uart.c
+romstage-y += ../common/wdt.c wdt.c
 
 ramstage-y += emi.c
 ramstage-$(CONFIG_SPI_FLASH) += spi.c
 ramstage-y += soc.c
 ramstage-y += ../common/timer.c
 ramstage-y += ../common/uart.c
+ramstage-y += ../common/wdt.c wdt.c
 
 CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include
 CPPFLAGS_common += -Isrc/soc/mediatek/common/include
diff --git a/src/soc/mediatek/mt8186/bootblock.c b/src/soc/mediatek/mt8186/bootblock.c
index f48e78c309..770c6031da 100644
--- a/src/soc/mediatek/mt8186/bootblock.c
+++ b/src/soc/mediatek/mt8186/bootblock.c
@@ -2,8 +2,10 @@
 
 #include <bootblock_common.h>
 #include <soc/mmu_operations.h>
+#include <soc/wdt.h>
 
 void bootblock_soc_init(void)
 {
 	mtk_mmu_init();
+	mtk_wdt_init();
 }
diff --git a/src/soc/mediatek/mt8186/wdt.c b/src/soc/mediatek/mt8186/wdt.c
new file mode 100644
index 0000000000..d0e13d98e9
--- /dev/null
+++ b/src/soc/mediatek/mt8186/wdt.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 3.4
+ */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/wdt.h>
+
+#define MTK_WDT_CLR_STATUS 0x22000000
+
+void mtk_wdt_clr_status(uint32_t wdt_sta)
+{
+	write32(&mtk_wdt->wdt_mode, wdt_sta | MTK_WDT_CLR_STATUS);
+}