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soc/amd/stoneyridge/southbridge: move PSP BAR hide bit to its register 

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9838e2433004686e3ea82724c55066bcee1f019
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Felix Held 2021-01-29 22:15:08 +01:00
parent abde3ff503
commit 5ddcfe5ec1
1 changed files with 2 additions and 2 deletions
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4
src/soc/amd/stoneyridge/include/soc/southbridge.h
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@ -202,10 +202,10 @@ void soc_enable_psp_early(void);
#define PSP_MAILBOX_OFFSET 0x70 /* offset from BAR3 value */
#define PSP_BAR_ENABLES 0x48
#define PSP_MAILBOX_BAR_EN 0x10
#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */
#define PSP_MAILBOX_BAR_EN BIT(4)
#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */
#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */
typedef struct aoac_devs {
unsigned int :5;