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mb/google/brya/var/primus{4es}: add delay time to rtd3-cold 

This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.We checked power on sequence requires enable pin prior to reset pin, added delay to meet the sequence and test passed on various eMMC SKUs.Base on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2.

BUG=b:224648680
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
          test suspend stress 2500 cycles passed on primus

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Terry Chen 2022-03-21 11:06:04 +08:00 committed by Tim Wawrzynczak
parent ad63eabe3a
commit 5deefc8bd3
2 changed files with 4 additions and 0 deletions
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2
src/mainboard/google/brya/variants/primus/overridetree.cb
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@ -147,6 +147,8 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
register "srcclk_pin" = "6"
register "reset_delay_ms" = "50"
register "enable_delay_ms" = "20"
device generic 0 alias emmc_rtd3 on end
end
# Enable PCIe-to-eMMC bridge PCIE 3 using clk 6

2
src/mainboard/google/brya/variants/primus4es/overridetree.cb
View File

@ -141,6 +141,8 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
register "srcclk_pin" = "6"
register "reset_delay_ms" = "50"
register "enable_delay_ms" = "20"
device generic 0 alias emmc_rtd3 on end
end
# Enable PCIe-to-eMMC bridge PCIE 3 using clk 6