soc/amd/picasso/pci_devs: Update pci_devs.h with correct values
This is a squash of the following commits. The original values were wrong, and had confusing naming. soc/amd/picasso: Get rid of *_DEVID from pci_devs.h Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I203449499840bf0a6df8bd879fb7d2e75a16b284 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153714 src/amd/picasso: Update PCI bridge devices Orignal-Change-Id: I1fa9d52ce113eacdc5c9ba31ab46b6428a7d6ca9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Zork: Reorganizing ACPI and adding PCI bridge configs Signed-off-by: Pranay Shoroff <pshoroff@google.com> Original-Change-Id: I1e2095567525f302dfd0bce8e39001250523180b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2063536 soc/amd/picasso: Fix soc_acpi_name() to use devfn instead of devid Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I2486e7e0059e0528f53d5a158c9328636563fe93 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153712 BUG=b:147042464 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I91bf7f9edcddf03027f8fdcaadf4e290ece10df5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Furquan Shaikh
Felix Held
parent
4732f23a1f
commit
5df9a04640
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@ -2,6 +2,7 @@
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#include <bootstate.h>
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#include <cpu/amd/mtrr.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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@ -50,30 +51,58 @@ const char *soc_acpi_name(const struct device *dev)
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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switch (dev->path.pci.devfn) {
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case PCIE0_DEVFN:
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return "PBR4";
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case PCIE1_DEVFN:
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return "PBR5";
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case PCIE2_DEVFN:
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return "PBR6";
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case PCIE3_DEVFN:
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return "PBR7";
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case PCIE4_DEVFN:
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return "PBR8";
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case HDA1_DEVFN:
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return "AZHD";
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case LPC_DEVFN:
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return "LPCB";
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case SMBUS_DEVFN:
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return "SBUS";
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case XHCI0_DEVFN:
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return "XHC0";
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case XHCI1_DEVFN:
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return "XHC1";
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default:
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return NULL;
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if (dev->bus->dev->path.type == DEVICE_PATH_DOMAIN) {
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switch (dev->path.pci.devfn) {
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case GNB_DEVFN:
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return "GNB";
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case IOMMU_DEVFN:
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return "IOMM";
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case PCIE_GPP_0_DEVFN:
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return "PBR0";
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case PCIE_GPP_1_DEVFN:
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return "PBR1";
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case PCIE_GPP_2_DEVFN:
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return "PBR2";
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case PCIE_GPP_3_DEVFN:
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return "PBR3";
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case PCIE_GPP_4_DEVFN:
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return "PBR4";
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case PCIE_GPP_5_DEVFN:
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return "PBR5";
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case PCIE_GPP_6_DEVFN:
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return "PBR6";
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case PCIE_GPP_A_DEVFN:
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return "PBRA";
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case PCIE_GPP_B_DEVFN:
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return "PBRB";
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case LPC_DEVFN:
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return "LPCB";
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case SMBUS_DEVFN:
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return "SBUS";
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default:
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printk(BIOS_WARNING, "Unknown root PCI device: dev: %d, fn: %d\n",
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PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
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return NULL;
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}
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}
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if (dev->bus->dev->path.type == DEVICE_PATH_PCI
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&& dev->bus->dev->path.pci.devfn == PCIE_GPP_A_DEVFN) {
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switch (dev->path.pci.devfn) {
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case XHCI0_DEVFN:
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return "XHC0";
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case XHCI1_DEVFN:
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return "XHC1";
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default:
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printk(BIOS_WARNING, "Unknown Bus A PCI device: dev: %d, fn: %d\n",
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PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
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return NULL;
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}
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}
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printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n",
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PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
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return NULL;
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};
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struct device_operations pci_domain_ops = {
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@ -15,79 +15,78 @@
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/* GNB Root Complex */
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#define GNB_DEV 0x0
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#define GNB_FUNC 0
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#define GNB_DEVID 0x1576
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#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC)
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#define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC)
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/* IOMMU */
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#define IOMMU_DEV 0x0
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#define IOMMU_FUNC 2
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#define IOMMU_DEVID 0x1577
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#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)
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#define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC)
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/* Internal Graphics */
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#define GFX_DEV 0x1
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#define GFX_FUNC 0
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#define GFX_DEVID 0x15d8
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#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC)
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#define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC)
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/* PCIe GPP Bridges 0 - 6 */
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#define PCIE_HOST_BRIDGE_06_DEV 0x1
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/* HD Audio 0 */
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#define HDA0_DEV 0x1
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#define HDA0_FUNC 1
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#define HDA0_DEVID 0x15b3
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#define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC)
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#define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC)
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#define PCIE_GPP_0_FUNC 1
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#define PCIE_GPP_0_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_0_FUNC)
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#define SOC_GPP_0_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_0_FUNC)
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/* Host Bridge */
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#define HOST_DEV 0x2
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#define HOST_FUNC 0
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#define HOST_DEVID 0x157b
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#define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC)
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#define SOC_HOST_DEV _SOC_DEV(HOST_DEV, HOST_FUNC)
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#define PCIE_GPP_1_FUNC 2
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#define PCIE_GPP_1_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_1_FUNC)
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#define SOC_GPP_1_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_1_FUNC)
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/* PCIe GPP Bridge 0 */
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#define PCIE0_DEV 0x2
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#define PCIE0_FUNC 1
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#define PCIE0_DEVID 0x157c
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#define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC)
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#define SOC_PCIE0_DEV _SOC_DEV(PCIE0_DEV, PCIE0_FUNC)
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#define PCIE_GPP_2_FUNC 3
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#define PCIE_GPP_2_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_2_FUNC)
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#define SOC_GPP_2_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_2_FUNC)
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/* PCIe GPP Bridge 1 */
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#define PCIE1_DEV 0x2
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#define PCIE1_FUNC 2
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#define PCIE1_DEVID 0x157c
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#define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC)
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#define SOC_PCIE1_DEV _SOC_DEV(PCIE1_DEV, PCIE1_FUNC)
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#define PCIE_GPP_3_FUNC 4
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#define PCIE_GPP_3_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_3_FUNC)
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#define SOC_GPP_3_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_3_FUNC)
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/* PCIe GPP Bridge 2 */
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#define PCIE2_DEV 0x2
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#define PCIE2_FUNC 3
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#define PCIE2_DEVID 0x157c
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#define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC)
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#define SOC_PCIE2_DEV _SOC_DEV(PCIE2_DEV, PCIE2_FUNC)
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#define PCIE_GPP_4_FUNC 5
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#define PCIE_GPP_4_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_4_FUNC)
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#define SOC_GPP_4_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_4_FUNC)
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/* PCIe GPP Bridge 3 */
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#define PCIE3_DEV 0x2
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#define PCIE3_FUNC 4
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#define PCIE3_DEVID 0x157c
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#define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC)
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#define SOC_PCIE3_DEV _SOC_DEV(PCIE3_DEV, PCIE3_FUNC)
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#define PCIE_GPP_5_FUNC 6
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#define PCIE_GPP_5_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_5_FUNC)
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#define SOC_GPP_5_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_5_FUNC)
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/* PCIe GPP Bridge 4 */
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#define PCIE4_DEV 0x2
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#define PCIE4_FUNC 5
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#define PCIE4_DEVID 0x157c
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#define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC)
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#define SOC_PCIE4_DEV _SOC_DEV(PCIE4_DEV, PCIE4_FUNC)
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#define PCIE_GPP_6_FUNC 7
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#define PCIE_GPP_6_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_6_FUNC)
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#define SOC_GPP_6_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_6_FUNC)
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/* HD Audio 1 */
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#define HDA1_DEV 0x9
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#define HDA1_FUNC 2
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#define HDA1_DEVID 0x157a
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#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC)
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#define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC)
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/* PCIe GPP Bridges to Bus A and Bus B devices */
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#define PCIE_HOST_BRIDGE_AB_DEV 0x8
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#define PCIE_GPP_A_FUNC 1
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#define PCIE_GPP_A_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_AB_DEV, PCIE_GPP_A_FUNC)
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#define SOC_PCIE_GPP_A_DEV _SOC_DEV(PCIE_HOST_BRIDGE_AB_DEV, PCIE_GPP_A_FUNC)
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#define GFX_DEV 0x0
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#define GFX_FUNC 0
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#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC)
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#define XHCI0_DEV 0x0
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#define XHCI0_FUNC 3
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#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC)
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#define XHCI1_DEV 0x0
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#define XHCI1_FUNC 4
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#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC)
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#define AUDIO_DEV 0x0
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#define AUDIO_FUNC 5
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#define AUDIO_DEVFN PCI_DEVFN(AUDIO_DEV, AUDIO_FUNC)
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#define HD_AUDIO_DEV 0x0
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#define HD_AUDIO_FUNC 6
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#define HD_AUDIO_DEVFN PCI_DEVFN(HD_AUDIO_DEV, HD_AUDIO_FUNC)
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#define PCIE_GPP_B_FUNC 2
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#define PCIE_GPP_B_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_AB_DEV, PCIE_GPP_B_FUNC)
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#define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_HOST_BRIDGE_AB_DEV, PCIE_GPP_B_FUNC)
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#define SATA_DEV 0x0
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#define SATA_FUNC 0
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#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC)
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/* Data Fabric functions */
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#define DF_DEV 0x18
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@ -113,40 +112,15 @@
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#define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6)
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#define SOC_DF_F6_DEV _SOC_DEV(DF_DEV, 6)
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/* USB 3.1 */
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#define XHCI0_DEV 0x0
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#define XHCI0_FUNC 3
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#define XHCI0_DEVID 0x15e0
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#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC)
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#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC)
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/* USB 3.1 */
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#define XHCI1_DEV 0x0
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#define XHCI1_FUNC 4
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#define XHCI1_DEVID 0x15e1
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#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC)
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#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC)
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/* SATA */
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#define SATA_DEV 0x11
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#define SATA_FUNC 0
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#define SATA_IDE_DEVID 0x7900
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#define AHCI_DEVID_MS 0x7901
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#define AHCI_DEVID_AMD 0x7904
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#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC)
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#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC)
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/* SMBUS */
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#define SMBUS_DEV 0x14
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#define SMBUS_FUNC 0
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#define SMBUS_DEVID 0x790b
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#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
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#define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC)
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/* LPC BUS */
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#define PCU_DEV 0x14
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#define LPC_FUNC 3
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#define LPC_DEVID 0x790e
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#define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC)
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#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC)
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