mb/amd/south_station: Convert to ASL 2.0 syntax
Generated 'build/dsdt.dsl' files are identical. Change-Id: I52c33679fbb7e9807423fc0fcc470e54105013db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46151 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
Kyösti Mälkki
parent
94bcbca32f
commit
5e03bd4f6d
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@ -50,11 +50,11 @@ OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
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Method(GTTM, 1) /* get total time*/
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{
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Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
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Increment(Local0)
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Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
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Increment(Local1)
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Return(Multiply(30, Add(Local0, Local1)))
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Local0 = Arg0 & 0x0F /* Recovery Width */
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Local0++
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Local1 = Arg0 >> 4 /* Command Width */
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Local1++
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Return(30 * (Local0 + Local1))
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}
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Device(PRID)
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@ -76,30 +76,30 @@ Device(PRID)
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CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
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/* Just return if the channel is disabled */
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If(And(PPCR, 0x01)) { /* primary PIO control */
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If (PPCR & 0x01) { /* primary PIO control */
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Return(OTBF)
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}
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/* Always tell them independent timing available and IOChannelReady used on both drives */
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Or(BFFG, 0x1A, BFFG)
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BFFG |= 0x1A
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Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
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Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
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PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing to PIO spd0 */
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PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing to PIO spd1 */
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If(And(PDCR, 0x01)) { /* It's under UDMA mode */
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Or(BFFG, 0x01, BFFG)
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Store(DerefOf(Index(UDTT, PDMM)), DSD0)
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If (PDCR & 0x01) { /* It's under UDMA mode */
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BFFG |= 0x01
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DSD0 = DerefOf(UDTT [PDMM])
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}
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Else {
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Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
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DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing, DmaSpd0 */
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}
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If(And(PDCR, 0x02)) { /* It's under UDMA mode */
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Or(BFFG, 0x04, BFFG)
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Store(DerefOf(Index(UDTT, PDSM)), DSD1)
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If (PDCR & 0x02) { /* It's under UDMA mode */
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BFFG |= 0x04
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DSD1 = DerefOf(UDTT [PDSM])
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}
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Else {
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Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
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DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing, DmaSpd0 */
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}
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Return(OTBF) /* out buffer */
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@ -120,35 +120,35 @@ Device(PRID)
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CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
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CreateDwordField(INBF, 16, BFFG) /*buffer flag */
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Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
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Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
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Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
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Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
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Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
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PPMM = Local0 % 5 /* Primary PIO master Mode */
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Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
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PPSM = Local1 % 5 /* Primary PIO slave Mode */
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Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
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Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
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PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
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PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
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If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
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Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
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Divide(Local0, 7, PDMM,)
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Or(PDCR, 0x01, PDCR)
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If (BFFG & 0x01) { /* Drive 0 is under UDMA mode */
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Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
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PDMM = Local0 % 7
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PDCR |= 0x01
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}
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Else {
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If(LNotEqual(DSD0, 0xFFFFFFFF)) {
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Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
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Store(DerefOf(Index(MDRT, Local0)), PMTM)
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If (DSD0 != 0xFFFFFFFF) {
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Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
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PMTM = DerefOf(MDRT [Local0])
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}
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}
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If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
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Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
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Divide(Local0, 7, PDSM,)
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Or(PDCR, 0x02, PDCR)
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If (BFFG & 0x04) { /* Drive 1 is under UDMA mode */
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Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
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PDSM = Local0 % 7
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PDCR |= 0x02
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}
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Else {
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If(LNotEqual(DSD1, 0xFFFFFFFF)) {
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Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
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Store(DerefOf(Index(MDRT, Local0)), PMTS)
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If (DSD1 != 0xFFFFFFFF) {
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Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
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PMTS = DerefOf(MDRT [Local0])
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}
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}
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/* Return(INBF) */
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@ -168,21 +168,19 @@ Device(PRID)
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CreateByteField(CMBF, 12, CMDB)
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CreateByteField(CMBF, 19, CMDC)
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Store(0xA0, CMDA)
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Store(0xA0, CMDB)
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Store(0xA0, CMDC)
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CMDA = 0xA0
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CMDB = 0xA0
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CMDC = 0xA0
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Or(PPMM, 0x08, POMD)
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POMD = PPMM | 0x08
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If(And(PDCR, 0x01)) {
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Or(PDMM, 0x40, DMMD)
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If (PDCR & 0x01) {
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DMMD = PDMM | 0x40
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}
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Else {
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Store(Match
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(MDTT, MLE, GTTM(PMTM),
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MTR, 0, 0), Local0)
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If(LLess(Local0, 3)) {
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Or(0x20, Local0, DMMD)
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Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
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If (Local0 < 3) {
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DMMD = Local0 | 0x20
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}
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}
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Return(CMBF)
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@ -204,21 +202,19 @@ Device(PRID)
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CreateByteField(CMBF, 12, CMDB)
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CreateByteField(CMBF, 19, CMDC)
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Store(0xB0, CMDA)
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Store(0xB0, CMDB)
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Store(0xB0, CMDC)
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CMDA = 0xB0
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CMDB = 0xB0
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CMDC = 0xB0
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Or(PPSM, 0x08, POMD)
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POMD = PPSM | 0x08
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If(And(PDCR, 0x02)) {
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Or(PDSM, 0x40, DMMD)
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If (PDCR & 0x02) {
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DMMD = PDSM | 0x40
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}
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Else {
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Store(Match
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(MDTT, MLE, GTTM(PMTS),
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MTR, 0, 0), Local0)
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If(LLess(Local0, 3)) {
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Or(0x20, Local0, DMMD)
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Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
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If (Local0 < 3) {
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DMMD = Local0 | 0x20
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}
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}
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Return(CMBF)
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@ -18,20 +18,20 @@ Name(PICM, One) /* Assume APIC */
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Scope(\_SB) {
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Method(OSFL, 0){
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if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
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if (OSVR != Ones) {Return (OSVR)} /* OS version was already detected */
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if(CondRefOf(\_OSI))
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{
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Store(1, OSVR) /* Assume some form of XP */
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OSVR = 1 /* Assume some form of XP */
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if (\_OSI("Windows 2006")) /* Vista */
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{
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Store(2, OSVR)
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OSVR = 2
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}
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} else {
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If (WCMP(\_OS,"Linux")) {
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Store(3, OSVR) /* Linux */
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OSVR = 3 /* Linux */
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} Else {
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Store(4, OSVR) /* Gotta be WinCE */
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OSVR = 4 /* Gotta be WinCE */
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}
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}
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Return(OSVR)
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@ -35,7 +35,7 @@ Device(PMRY)
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Device(PMST) {
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Name(_ADR, 0)
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Method(_STA,0) {
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if (LGreater(P0IS,0)) {
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if (P0IS > 0) {
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return (0x0F) /* sata is visible */
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}
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else {
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@ -48,7 +48,7 @@ Device(PMRY)
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{
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Name(_ADR, 1)
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Method(_STA,0) {
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if (LGreater(P1IS,0)) {
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if (P1IS > 0) {
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return (0x0F) /* sata is visible */
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}
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else {
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@ -70,7 +70,7 @@ Device(SEDY)
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{
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Name(_ADR, 0)
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Method(_STA,0) {
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if (LGreater(P2IS,0)) {
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if (P2IS > 0) {
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return (0x0F) /* sata is visible */
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}
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else {
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@ -83,7 +83,7 @@ Device(SEDY)
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{
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Name(_ADR, 1)
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Method(_STA,0) {
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if (LGreater(P3IS,0)) {
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if (P3IS > 0) {
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return (0x0F) /* sata is visible */
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}
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else {
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@ -97,35 +97,35 @@ Device(SEDY)
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Scope(\_GPE) {
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Method(_L1F,0x0,NotSerialized) {
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if (\_SB.P0PR) {
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if (LGreater(\_SB.P0IS,0)) {
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if (\_SB.P0IS > 0) {
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sleep(32)
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}
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Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
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store(one, \_SB.P0PR)
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\_SB.P0PR = 1
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}
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if (\_SB.P1PR) {
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if (LGreater(\_SB.P1IS,0)) {
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if (\_SB.P1IS > 0) {
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sleep(32)
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}
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Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
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store(one, \_SB.P1PR)
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\_SB.P1PR = 1
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}
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if (\_SB.P2PR) {
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if (LGreater(\_SB.P2IS,0)) {
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if (\_SB.P2IS > 0) {
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sleep(32)
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}
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Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
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store(one, \_SB.P2PR)
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\_SB.P2PR = 1
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}
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if (\_SB.P3PR) {
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if (LGreater(\_SB.P3IS,0)) {
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if (\_SB.P3IS > 0) {
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sleep(32)
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}
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Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
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store(one, \_SB.P3PR)
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\_SB.P3PR = 1
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}
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}
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}
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@ -26,23 +26,23 @@ Method(\_PTS, 1) {
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/* DBGO("\n") */
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/* Don't allow PCIRST# to reset USB */
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if (LEqual(Arg0,3)){
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Store(0,URRE)
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if (Arg0 == 3){
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URRE = 0
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}
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/* Clear sleep SMI status flag and enable sleep SMI trap. */
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/*Store(One, CSSM)
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Store(One, SSEN)*/
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/*CSSM = 1
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SSEN = 1*/
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/* On older chips, clear PciExpWakeDisEn */
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/*if (LLessEqual(\_SB.SBRI, 0x13)) {
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* Store(0,\_SB.PWDE)
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/*if (\_SB.SBRI <= 0x13) {
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* \_SB.PWDE = 0
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*}
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*/
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/* Clear wake status structure. */
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Store(0, Index(WKST,0))
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Store(0, Index(WKST,1))
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WKST [0] = 0
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WKST [1] = 0
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} /* End Method(\_PTS) */
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/*
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@ -67,21 +67,21 @@ Method(\_WAK, 1) {
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/* DBGO(" to S0\n") */
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/* Re-enable HPET */
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Store(1,HPDE)
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HPDE = 1
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/* Restore PCIRST# so it resets USB */
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if (LEqual(Arg0,3)){
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Store(1,URRE)
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if (Arg0 == 3){
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URRE = 1
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}
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/* Arbitrarily clear PciExpWakeStatus */
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Store(PWST, Local1)
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Store(Local1, PWST)
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Local1 = PWST
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PWST = Local1
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/* if (DeRefOf(Index(WKST,0))) {
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* Store(0, Index(WKST,1))
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/* if (DeRefOf(WKST [0])) {
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* WKST [1] = 0
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* } else {
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* Store(Arg0, Index(WKST,1))
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* WKST [1] = Arg0
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* }
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*/
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Return(WKST)
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@ -14,134 +14,134 @@ Name(UOM9, 6)
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Method(UCOC, 0) {
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Sleep(20)
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Store(0x13,CMTI)
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Store(0,GPSL)
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CMTI = 0x13
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GPSL = 0
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}
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/* USB Port 0 overcurrent uses Gpm 0 */
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If(LLessEqual(UOM0,9)) {
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If (UOM0 <= 9) {
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Scope (\_GPE) {
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Method (_L13) {
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UCOC()
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if(LEqual(GPB0,PLC0)) {
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Not(PLC0,PLC0)
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Store(PLC0, \_SB.PT0D)
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if (GPB0 == PLC0) {
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PLC0 = ~PLC0
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\_SB.PT0D = PLC0
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}
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}
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}
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}
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/* USB Port 1 overcurrent uses Gpm 1 */
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If (LLessEqual(UOM1,9)) {
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If (UOM1 <= 9) {
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Scope (\_GPE) {
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Method (_L14) {
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UCOC()
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if (LEqual(GPB1,PLC1)) {
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Not(PLC1,PLC1)
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Store(PLC1, \_SB.PT1D)
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if (GPB1 == PLC1) {
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PLC1 = ~PLC1
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\_SB.PT1D = PLC1
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}
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}
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}
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}
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/* USB Port 2 overcurrent uses Gpm 2 */
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If (LLessEqual(UOM2,9)) {
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If (UOM2 <= 9) {
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Scope (\_GPE) {
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Method (_L15) {
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UCOC()
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if (LEqual(GPB2,PLC2)) {
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Not(PLC2,PLC2)
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Store(PLC2, \_SB.PT2D)
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if (GPB2 == PLC2) {
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PLC2 = ~PLC2
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\_SB.PT2D = PLC2
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}
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}
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}
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}
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/* USB Port 3 overcurrent uses Gpm 3 */
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If (LLessEqual(UOM3,9)) {
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If (UOM3 <= 9) {
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Scope (\_GPE) {
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Method (_L16) {
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UCOC()
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if (LEqual(GPB3,PLC3)) {
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Not(PLC3,PLC3)
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Store(PLC3, \_SB.PT3D)
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if (GPB3 == PLC3) {
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PLC3 = ~PLC3
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\_SB.PT3D = PLC3
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}
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}
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}
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}
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/* USB Port 4 overcurrent uses Gpm 4 */
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If (LLessEqual(UOM4,9)) {
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If (UOM4 <= 9) {
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Scope (\_GPE) {
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Method (_L19) {
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UCOC()
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if (LEqual(GPB4,PLC4)) {
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Not(PLC4,PLC4)
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Store(PLC4, \_SB.PT4D)
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if (GPB4 == PLC4) {
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PLC4 = ~PLC4
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\_SB.PT4D = PLC4
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}
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}
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}
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}
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/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
If (UOM5 <= 9) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
if (GPB5 == PLC5) {
|
||||
PLC5 = ~PLC5
|
||||
\_SB.PT5D = PLC5
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
If (UOM6 <= 9) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
if (GPB6 == PLC6) {
|
||||
PLC6 = ~PLC6
|
||||
\_SB.PT6D = PLC6
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
If (UOM7 <= 9) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
if (GPB7 == PLC7) {
|
||||
PLC7 = ~PLC7
|
||||
\_SB.PT7D = PLC7
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
If (UOM8 <= 9) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
if (G8IS == PLC8) {
|
||||
PLC8 = ~PLC8
|
||||
\_SB.PT8D = PLC8
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
If (UOM9 <= 9) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
if (G9IS == 0) {
|
||||
\_SB.PT9D = 1
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue