soc/intel/quark: Switch to using serial routines for FSP
Switch from passing FSP the serial port address to passing FSP the serial port output routine. This enables coreboot to use any UART in the system and also log the FSP output. TEST=Build and run on Galileo Gen2 Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16105 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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Lee Leahy
parent
00a38a4a9e
commit
5e07a7e474
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@ -53,7 +53,7 @@ struct FSP_M_CONFIG {
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/** Offset 0x0048 - SerialPortBaseAddress
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Debug serial port base address set by BIOS. Zero disables debug serial output.
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**/
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uint32_t SerialPortBaseAddress;
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uint32_t Reserved_48;
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/** Offset 0x004C - tRAS
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ACT to PRE command period in picoseconds.
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@ -199,6 +199,18 @@ struct FSP_M_CONFIG {
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uint32_t MrcDataLength;
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/** Offset 0x0080
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**/
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uint32_t SerialPortPollForChar;
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/** Offset 0x0084
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**/
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uint32_t SerialPortReadChar;
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/** Offset 0x0088
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**/
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uint32_t SerialPortWriteChar;
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/** Offset 0x008C
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**/
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uint16_t UpdTerminator;
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} __attribute__((packed));
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@ -21,7 +21,6 @@
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#include "../chip.h"
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#include <fsp/memmap.h>
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#include <fsp/util.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/QuarkNcSocId.h>
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#include <soc/romstage.h>
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@ -120,8 +119,8 @@ void soc_memory_init_params(struct romstage_params *params,
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upd->RankMask = config->RankMask;
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upd->RmuBaseAddress = (uintptr_t)rmu_file;
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upd->RmuLength = rmu_file_len;
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upd->SerialPortBaseAddress = console_log_level(BIOS_SPEW)
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? UART_BASE_ADDRESS : 0;
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upd->SerialPortWriteChar = console_log_level(BIOS_SPEW)
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? (uintptr_t)fsp_write_line : 0;
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upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
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config->SmmTsegSize : 0;
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upd->SocRdOdtVal = config->SocRdOdtVal;
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@ -176,9 +175,15 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
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old->RmuBaseAddress, new->RmuBaseAddress);
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fsp_display_upd_value("RmuLength", sizeof(old->RmuLength),
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old->RmuLength, new->RmuLength);
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fsp_display_upd_value("SerialPortBaseAddress",
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sizeof(old->SerialPortBaseAddress),
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old->SerialPortBaseAddress, new->SerialPortBaseAddress);
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fsp_display_upd_value("SerialPortPollForChar",
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sizeof(old->SerialPortPollForChar),
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old->SerialPortPollForChar, new->SerialPortPollForChar);
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fsp_display_upd_value("SerialPortReadChar",
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sizeof(old->SerialPortReadChar),
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old->SerialPortReadChar, new->SerialPortReadChar);
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fsp_display_upd_value("SerialPortWriteChar",
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sizeof(old->SerialPortWriteChar),
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old->SerialPortWriteChar, new->SerialPortWriteChar);
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fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize),
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old->SmmTsegSize, new->SmmTsegSize);
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fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal),
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@ -20,7 +20,6 @@
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#include "../chip.h"
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#include <cpu/x86/cache.h>
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#include <fsp/util.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/romstage.h>
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@ -161,8 +160,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd)
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upd->RankMask = config->RankMask;
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upd->RmuBaseAddress = (uintptr_t)rmu_file;
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upd->RmuLength = rmu_file_len;
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upd->SerialPortBaseAddress = console_log_level(BIOS_SPEW)
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? UART_BASE_ADDRESS : 0;
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upd->SerialPortWriteChar = console_log_level(BIOS_SPEW)
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? (uintptr_t)fsp_write_line : 0;
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upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
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config->SmmTsegSize : 0;
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upd->SocRdOdtVal = config->SocRdOdtVal;
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@ -88,7 +88,7 @@ typedef struct {
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UINT32 RmuLength;
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/** Offset 0x0030
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**/
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UINT32 SerialPortBaseAddress;
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UINT32 Reserved_30;
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/** Offset 0x0034
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**/
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UINT32 tRAS;
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@ -175,17 +175,26 @@ typedef struct {
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UINT32 MrcDataLength;
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/** Offset 0x0068
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**/
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UINT8 ReservedMemoryInitUpd[8];
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UINT32 SerialPortPollForChar;
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/** Offset 0x006C
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**/
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UINT32 SerialPortReadChar;
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/** Offset 0x0070
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**/
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UINT32 SerialPortWriteChar;
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/** Offset 0x0074
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**/
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UINT8 ReservedMemoryInitUpd[12];
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} MEMORY_INIT_UPD;
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typedef struct {
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/** Offset 0x0070
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/** Offset 0x0080
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**/
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UINT64 Signature;
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/** Offset 0x0078
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/** Offset 0x0088
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**/
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UINT64 Revision;
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/** Offset 0x0080
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/** Offset 0x0090
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**/
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UINT16 PcdRegionTerminator;
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} SILICON_INIT_UPD;
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@ -210,7 +219,7 @@ typedef struct _UPD_DATA_REGION {
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/** Offset 0x0018
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**/
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MEMORY_INIT_UPD MemoryInitUpd;
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/** Offset 0x0070
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/** Offset 0x0080
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**/
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SILICON_INIT_UPD SiliconInitUpd;
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} UPD_DATA_REGION;
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