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mb/google/zork: adjust the eDP panel power sequence 

set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight
on and vary backlight.

BUG=b:171269338
BRANCH=zork
TEST=Build; Verify the UPD was passed to system integrated table; measure
the power on sequence on dalboz

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Chris Wang 2020-12-23 04:42:26 +08:00 committed by Patrick Georgi
parent 3ec3cb82f9
commit 5e0db41602
1 changed files with 12 additions and 0 deletions
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12
src/mainboard/google/zork/variants/vilboz/overridetree.cb
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@ -26,6 +26,18 @@ chip soc/amd/picasso
# eDP phy tuning settings # eDP phy tuning settings
register "dp_phy_override" = "ENABLE_EDP_TUNINGSET" register "dp_phy_override" = "ENABLE_EDP_TUNINGSET"
# eDP power sequence. all pwr sequence numbers below are in uint of 4ms,
# and "0" as default value
register "edp_pwr_adjust_enable" = "1"
register "pwron_digon_to_de" = "0"
register "pwron_de_to_varybl" = "0"
register "pwrdown_varybloff_to_de" = "0"
register "pwrdown_de_to_digoff" = "0"
register "pwroff_delay" = "0"
register "pwron_varybl_to_blon" = "5"
register "pwrdown_bloff_to_varybloff" = "5"
register "min_allowed_bl_level" = "0"
register "edp_tuningset" = "{ register "edp_tuningset" = "{
.dp_vs_pemph_level = 0x0, .dp_vs_pemph_level = 0x0,
.deemph_6db4 = 0x004b, .deemph_6db4 = 0x004b,