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soc/amd/stoneyridge: clean up global NVS 

Remove the unused fields that were previously used for PCNT and PWRS.
The LIDS field is only used in the ACPI code, but keep if for now, since
it would require a bigger rework to remove it from the global NVS.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b172214998818f841f5694f47815eddfaf9deaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72139
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2023-01-20 19:57:40 +01:00
parent 4a5f2e9e96
commit 5e2d9c0979
2 changed files with 15 additions and 19 deletions
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16
src/soc/amd/stoneyridge/acpi/globalnvs.asl
View File

@ -9,15 +9,13 @@
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
, 8, // 0x00 - Processor Count
LIDS, 8, // 0x01 - LID State
, 8, // 0x02 - AC Power State
CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console
PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index
GPEI, 64, // 0x0f - 0x16 - GPE Wake Source
TMPS, 8, // 0x17 - Temperature Sensor ID
TCRT, 8, // 0x18 - Critical Threshold
TPSV, 8, // 0x19 - Passive Threshold
LIDS, 8, // 0x00 - LID State
CBMC, 32, // 0x01 - 0x04 - coreboot Memory Console
PM1I, 64, // 0x05 - 0x0c - System Wake Source - PM1 Index
GPEI, 64, // 0x0d - 0x14 - GPE Wake Source
TMPS, 8, // 0x15 - Temperature Sensor ID
TCRT, 8, // 0x16 - Critical Threshold
TPSV, 8, // 0x17 - Passive Threshold
Offset (0x20), // 0x20 - AOAC Device Enables
, 5,
IC0E, 1, // I2C0, 5

18
src/soc/amd/stoneyridge/include/soc/nvs.h
View File

@ -14,16 +14,14 @@
struct __packed global_nvs {
/* Miscellaneous */
uint8_t unused_was_pcnt; /* 0x00 - Processor Count */
uint8_t lids; /* 0x01 - LID State */
uint8_t unused_was_pwrs; /* 0x02 - AC Power State */
uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */
uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */
uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */
uint8_t tmps; /* 0x17 - Temperature Sensor ID */
uint8_t tcrt; /* 0x18 - Critical Threshold */
uint8_t tpsv; /* 0x19 - Passive Threshold */
uint8_t pad1[6];
uint8_t lids; /* 0x00 - LID State */
uint32_t cbmc; /* 0x01 - 0x04 - coreboot Memory Console */
uint64_t pm1i; /* 0x05 - 0x0c - System Wake Source - PM1 Index */
uint64_t gpei; /* 0x0d - 0x14 - GPE Wake Source */
uint8_t tmps; /* 0x15 - Temperature Sensor ID */
uint8_t tcrt; /* 0x16 - Critical Threshold */
uint8_t tpsv; /* 0x17 - Passive Threshold */
uint8_t pad1[8];
aoac_devs_t aoac; /* 0x20 - AOAC device enables */
uint16_t fw00; /* 0x24 - XhciFwRomAddr_Rom, Boot RAM */
uint16_t fw02; /* 0x26 - XhciFwRomAddr_Ram, Instr RAM */