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amd/stoneyridge: Replace BIT(n) in southbridge 

Use more descriptive #define values for the ACPI features and
register decoding.

Change-Id: Iaaf9f9bd5761001bc4bfe6b64a6c72b1f04844bd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22427
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Marshall Dawson 2017-11-10 09:59:56 -07:00 committed by Martin Roth
parent 7465b9dc8d
commit 5e2e74f981
1 changed files with 5 additions and 4 deletions
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9
src/soc/amd/stoneyridge/southbridge.c
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@ -61,10 +61,11 @@ static void sb_init_acpi_ports(void)
pm_write16(PM_ACPI_SMI_CMD, 0);
}
/* AcpiDecodeEnable, When set, SB uses the contents of the PM registers
* at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn
*/
pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2));
/* Decode ACPI registers and enable standard features */
pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD |
PM_ACPI_GLOBAL_EN |
PM_ACPI_RTC_EN_EN |
PM_ACPI_TIMER_EN_EN);
}
void southbridge_init(void *chip_info)