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nb/x4x: Do not enable IGD when not supported 

According to "Intel ® 4 Series Chipset Family datasheet" in the
description about GGC and DEVEN, CAPID0 bit46 is said to reflect the
presence of an internal graphic device. This would allow the P43 and
P45 chipset variants to work.

Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18515
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2017-03-05 10:57:02 +01:00 committed by Nico Huber
parent 2e7efe65a2
commit 5e3cb72a71
1 changed files with 14 additions and 7 deletions
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9
src/northbridge/intel/x4x/early_init.c
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@ -27,6 +27,7 @@
void x4x_early_init(void) void x4x_early_init(void)
{ {
u8 gfxsize;
const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */ /* Setup MCHBAR. */
@ -54,15 +55,21 @@ void x4x_early_init(void)
pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
pci_write_config8(d0f0, D0F0_PAM(6), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) {
/* Enable internal GFX */ /* Enable internal GFX */
pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
/* Set preallocated IGD size from cmos */ /* Set preallocated IGD size from cmos */
u8 gfxsize;
if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
/* 6 for 64MB, default if not set in cmos */ /* 6 for 64MB, default if not set in cmos */
gfxsize = 6; gfxsize = 6;
} }
pci_write_config16(d0f0, D0F0_GGC,
0x0100 | ((gfxsize + 1) << 4));
} else { /* Does not feature internal graphics */
pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN);
pci_write_config16(d0f0, D0F0_GGC, (1 << 1));
}
pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4)); pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4));
} }