mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable
This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD for WHL/CML SoC code to set this HECI1 chip config. Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -28,7 +28,7 @@ chip soc/intel/cannonlake
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# Enable System Agent dynamic frequency
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# Enable System Agent dynamic frequency
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register "SaGv" = "SaGv_Enabled"
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register "SaGv" = "SaGv_Enabled"
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# Enable heci communication
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# Enable heci communication
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register "HeciEnabled" = "1"
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register "HeciEnabled" = "0"
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# Enable Speed Shift Technology support
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# Enable Speed Shift Technology support
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register "speed_shift_enable" = "1"
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register "speed_shift_enable" = "1"
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# Enable S0ix
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# Enable S0ix
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@ -15,7 +15,7 @@ chip soc/intel/cannonlake
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# FSP configuration
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# FSP configuration
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register "SaGv" = "SaGv_Enabled"
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register "SaGv" = "SaGv_Enabled"
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register "HeciEnabled" = "1"
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register "HeciEnabled" = "0"
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register "SataSalpSupport" = "1"
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register "SataSalpSupport" = "1"
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register "SataMode" = "Sata_AHCI"
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register "SataMode" = "Sata_AHCI"
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register "SataPortsEnable[2]" = "1"
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register "SataPortsEnable[2]" = "1"
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@ -15,7 +15,7 @@ chip soc/intel/cannonlake
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# FSP configuration
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# FSP configuration
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register "SaGv" = "SaGv_Enabled"
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register "SaGv" = "SaGv_Enabled"
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register "HeciEnabled" = "1"
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register "HeciEnabled" = "0"
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register "SataSalpSupport" = "1"
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register "SataSalpSupport" = "1"
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register "SataMode" = "Sata_AHCI"
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register "SataMode" = "Sata_AHCI"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[0]" = "1"
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