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mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable 

This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD
for WHL/CML SoC code to set this HECI1 chip config.

Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2019-06-04 14:43:58 +05:30
parent a0368a0950
commit 5e5167ed04
3 changed files with 3 additions and 3 deletions
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2
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
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@ -28,7 +28,7 @@ chip soc/intel/cannonlake
# Enable System Agent dynamic frequency
register "SaGv" = "SaGv_Enabled"
# Enable heci communication
register "HeciEnabled" = "1"
register "HeciEnabled" = "0"
# Enable Speed Shift Technology support
register "speed_shift_enable" = "1"
# Enable S0ix

2
src/mainboard/google/sarien/variants/arcada/devicetree.cb
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@ -15,7 +15,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "HeciEnabled" = "1"
register "HeciEnabled" = "0"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"
register "SataPortsEnable[2]" = "1"

2
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -15,7 +15,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "HeciEnabled" = "1"
register "HeciEnabled" = "0"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"
register "SataPortsEnable[0]" = "1"