soc/intel/common: Set controller state to active in uart init
Set the controller state to D0 during the uart init sequence, this ensures the controller is up and active. One more argument "const struct device *dev" has been added to uart_lpss_init function. BUG=b:135941367 TEST=Verify no timeouts seen during UART controller enumeration sequence in CML, ICL and APL platforms Change-Id: Ie91b502a38d1a40a3dea3711b015b7a5b7ede2db Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34810 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -33,8 +33,11 @@
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extern const struct uart_gpio_pad_config uart_gpio_pads[];
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extern const int uart_max_index;
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static void uart_lpss_init(uintptr_t baseaddr)
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static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr)
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{
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/* Ensure controller is in D0 state */
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lpss_set_power_state(dev, STATE_D0);
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/* Take UART out of reset */
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lpss_reset_release(baseaddr);
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@ -79,7 +82,7 @@ void uart_common_init(const struct device *device, uintptr_t baseaddr)
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/* Enable memory access and bus master */
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pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE);
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uart_lpss_init(baseaddr);
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uart_lpss_init(device, baseaddr);
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}
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const struct device *uart_get_device(void)
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@ -231,7 +234,7 @@ static void uart_common_enable_resources(struct device *dev)
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base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF;
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if (base)
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uart_lpss_init(base);
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uart_lpss_init(dev, base);
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}
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}
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