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mb/intel/wtm2: Prepare devicetree for PCH split 

Tested with BUILD_TIMELESS=1, coreboot.rom remains identical.

Change-Id: I75d6594f9576c96a585526c652a070cb9616dbe9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46704
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-23 20:40:46 +02:00
parent f2a295a5b6
commit 5e60637ef6
1 changed files with 40 additions and 37 deletions
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17
src/mainboard/intel/wtm2/devicetree.cb
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@ -9,6 +9,15 @@ chip soc/intel/broadwell
# Enable DVI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
# chip soc/intel/broadwell/pch
register "alt_gp_smi_en" = "0x0000"
register "gpe0_en_1" = "0x00000400"
register "gpe0_en_2" = "0x00000000"
@ -18,13 +27,6 @@ chip soc/intel/broadwell
register "sata_port_map" = "0x2"
register "sio_acpi_mode" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 on end # Serial I/O DMA
@ -53,5 +55,6 @@ chip soc/intel/broadwell
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus
device pci 1f.6 on end # Thermal
# end
end
end