mb/intel/saddlebrook: migrate to FSP 2.0
This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) TODO: - testing Change-Id: I7481f3413de6780df01d9b769bd4f16d439f087c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35923 Reviewed-by: Michael Niewöhner Reviewed-by: Wim Vervoorn Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner
Nico Huber
parent
fda6cd6d28
commit
5e779f9a6c
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@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS
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select HAVE_CMOS_DEFAULT
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select MAINBOARD_USES_IFD_GBE_REGION
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select USE_INTEL_FSP_MP_INIT
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select MAINBOARD_USES_FSP2_0
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config IRQ_SLOT_COUNT
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int
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@ -61,82 +61,70 @@ chip soc/intel/skylake
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# VR Settings Configuration for 5 Domains
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------------+-------+
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# VR Settings Configuration for 4 Domains
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#+----------------+-----------+-----------+-------------+----------+
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#| Domain/Setting | SA | IA | GT Unsliced | GT |
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#+----------------+-----------+-----------+-------------+----------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-----------+-----------+-------------+----------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = 0x50, \
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.psi2threshold = 0x10, \
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.psi3threshold = 0x4, \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x1C, \
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.voltage_limit = 0x5F0 \
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(4),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(7),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = 0x50, \
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.psi2threshold = 0x14, \
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.psi3threshold = 0x4, \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x88, \
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.voltage_limit = 0x5F0 \
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}"
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register "domain_vr_config[VR_RING]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = 0x50, \
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.psi2threshold = 0x14, \
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.psi3threshold = 0x4, \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x88, \
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.voltage_limit = 0x5F0, \
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = 0x50, \
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.psi2threshold = 0x14, \
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.psi3threshold = 0x4, \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x8C ,\
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.voltage_limit = 0x5F0 \
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = 0x50, \
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.psi2threshold = 0x14, \
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.psi3threshold = 0x4, \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x8C, \
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.voltage_limit = 0x5F0 \
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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}"
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# Enable x1 slot
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@ -16,7 +16,7 @@
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#include <soc/ramstage.h>
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#include "gpio.h"
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void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
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void mainboard_silicon_init_params(FSP_SIL_UPD *params)
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{
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/* Configure pads prior to SiliconInit() in case there's any
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* dependencies during hardware initialization. */
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@ -24,10 +24,10 @@
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#include <spd_bin.h>
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void mainboard_memory_init_params(
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struct romstage_params *params,
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MEMORY_INIT_UPD *memory_params)
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
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struct spd_block blk = {
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.addr_map = { 0x50, 0x52, },
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};
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@ -36,26 +36,22 @@ void mainboard_memory_init_params(
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dump_spd_info(&blk);
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printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len);
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memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0];
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memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[1];
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printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
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memory_params->MemorySpdPtr00);
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printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",
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memory_params->MemorySpdPtr10);
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mem_cfg->MemorySpdPtr00 = (UINT32) blk.spd_array[0];
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mem_cfg->MemorySpdPtr10 = (UINT32) blk.spd_array[1];
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printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", mem_cfg->MemorySpdPtr00);
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printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", mem_cfg->MemorySpdPtr10);
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/*
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* Configure the DQ/DQS settings if required. In general the settings
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* should be set in the FSP flash image and should not need to be
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* changed.
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*/
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mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0,
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&memory_params->DqByteMapCh1);
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mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0,
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&memory_params->DqsMapCpu2DramCh1);
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mainboard_fill_rcomp_res_data(&memory_params->RcompResistor);
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mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget);
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mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, &mem_cfg->DqByteMapCh1);
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mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, &mem_cfg->DqsMapCpu2DramCh1);
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mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
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mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
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/* update spd length*/
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memory_params->MemorySpdDataLen = blk.len;
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memory_params->DqPinsInterleaved = TRUE;
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mem_cfg->MemorySpdDataLen = blk.len;
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mem_cfg->DqPinsInterleaved = TRUE;
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}
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