soc/intel/{apl,cnl}: Remove FSP CAR option
One of the reason FSP-T support had to be kept in place was for Intel Bootguard. This now works with native CAR code, so there is no reason to keep FSP-T as an option for these platforms. APL did not even build with FSP_CAR and finding FSP-T using walkcbfs was only recently fixed using FMAP, so there can be no doubt that this option was never used with coreboot master. Change-Id: I0d5844b5a6fd291a13e5f467f4fc682b17eafa63 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
481c52ddd5
commit
5e8c906cab
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@ -1,5 +1,6 @@
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config SOC_INTEL_APOLLOLAKE
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bool
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select INTEL_CAR_CQOS
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help
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Intel Apollolake support
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@ -13,6 +14,7 @@ config SOC_INTEL_GEMINILAKE
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select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
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select IDT_IN_EVERY_STAGE
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select PAGING_IN_CACHE_AS_RAM
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select INTEL_CAR_NEM
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help
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Intel GLK support
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@ -60,6 +62,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
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select SOC_INTEL_COMMON_BLOCK_ACPI
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select SOC_INTEL_COMMON_BLOCK_CAR
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select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_DSP
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@ -295,40 +298,6 @@ config NHLT_RT5682
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default n
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help
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Include DSP firmware settings for headset codec.
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choice
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prompt "Cache-as-ram implementation"
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default CAR_CQOS if !SOC_INTEL_GEMINILAKE
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default CAR_NEM
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help
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This option allows you to select how cache-as-ram (CAR) is set up.
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config CAR_NEM
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bool "Non-evict mode"
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select SOC_INTEL_COMMON_BLOCK_CAR
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select INTEL_CAR_NEM
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help
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Traditionally, CAR is set up by using Non-Evict mode. This method
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does not allow CAR and cache to co-exist, because cache fills are
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block in NEM mode.
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config CAR_CQOS
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bool "Cache Quality of Service"
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select SOC_INTEL_COMMON_BLOCK_CAR
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select INTEL_CAR_CQOS
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help
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Cache Quality of Service allows more fine-grained control of cache
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usage. As result, it is possible to set up portion of L2 cache for
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CAR and use remainder for actual caching.
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config USE_APOLLOLAKE_FSP_CAR
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bool "Use FSP CAR"
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select FSP_CAR
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help
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Use FSP APIs to initialize & tear down the Cache-As-Ram.
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endchoice
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#
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# Each bit in QOS mask controls this many bytes. This is calculated as:
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# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
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@ -10,7 +10,6 @@ subdirs-y += ../../../cpu/x86/cache
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bootblock-y += bootblock/bootblock.c
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bootblock-y += ../common/block/cpu/pm_timer_emulation.c
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bootblock-$(CONFIG_FSP_CAR) += fspcar.c
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bootblock-y += car.c
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bootblock-y += heci.c
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bootblock-y += gspi.c
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@ -1,32 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <FsptUpd.h>
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const FSPT_UPD temp_ram_init_params = {
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.FspUpdHeader = {
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.Signature = 0x545F4450554C5041ULL, /* 'APLUPD_T' */
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.Revision = 1,
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.Reserved = {0},
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},
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.FsptCommonUpd = {
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.Revision = 0,
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.Reserved = {0},
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/*
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* It is a requirement for firmware to have Firmware Interface Table
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* (FIT), which contains pointers to each microcode update.
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* The microcode update is loaded for all logical processors before
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* cpu reset vector.
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*
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* All SoC since Gen-4 has above mechanism in place to load microcode
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* even before hitting CPU reset vector. Hence skipping FSP-T loading
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* microcode after CPU reset by passing '0' value to
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* FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
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*/
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.MicrocodeRegionBase = 0,
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.MicrocodeRegionLength = 0,
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.CodeRegionBase =
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(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
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.CodeRegionLength = (uint32_t)CONFIG_ROM_SIZE,
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.Reserved1 = {0},
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},
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};
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@ -57,12 +57,12 @@ config CPU_SPECIFIC_OPTIONS
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select FSP_COMPRESS_FSP_S_LZMA
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select FSP_M_XIP
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select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
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select FSP_T_XIP if FSP_CAR
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select GENERIC_GPIO_LIB
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select HAVE_FSP_GOP
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select HAVE_FSP_LOGO_SUPPORT
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select HAVE_SMI_HANDLER
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select IDT_IN_EVERY_STAGE
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select INTEL_CAR_NEM_ENHANCED
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select INTEL_GMA_ACPI
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select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
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@ -80,6 +80,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
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select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
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select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
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select SOC_INTEL_COMMON_BLOCK_CAR
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select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
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select SOC_INTEL_COMMON_BLOCK_CNVI
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select SOC_INTEL_COMMON_BLOCK_CPU
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@ -276,32 +277,6 @@ config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
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This will enable a workaround in ASL _PS3 and _PS0 methods to force
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SD_PWR_ENABLE to stay low in D3.
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choice
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prompt "Cache-as-ram implementation"
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default USE_CANNONLAKE_CAR_NEM_ENHANCED
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help
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This option allows you to select how cache-as-ram (CAR) is set up.
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config USE_CANNONLAKE_CAR_NEM_ENHANCED
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bool "Enhanced Non-evict mode"
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select SOC_INTEL_COMMON_BLOCK_CAR
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select INTEL_CAR_NEM_ENHANCED
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help
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A current limitation of NEM (Non-Evict mode) is that code and data
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sizes are derived from the requirement to not write out any modified
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cache line. With NEM, if there is no physical memory behind the
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cached area, the modified data will be lost and NEM results will be
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inconsistent. ENHANCED NEM guarantees that modified data is always
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kept in cache while clean data is replaced.
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config USE_CANNONLAKE_FSP_CAR
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bool "Use FSP CAR"
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select FSP_CAR
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help
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Use FSP APIs to initialize and tear down the Cache-As-Ram.
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endchoice
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config FSP_HEADER_PATH
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default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
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default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE_1
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@ -12,38 +12,6 @@
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#include <soc/iomap.h>
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#include <soc/pch.h>
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#if CONFIG(FSP_CAR)
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#include <FsptUpd.h>
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const FSPT_UPD temp_ram_init_params = {
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.FspUpdHeader = {
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.Signature = 0x545F4450554C4643ULL, /* 'CFLUPD_T' */
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.Revision = 1,
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.Reserved = {0},
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},
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.FsptCoreUpd = {
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/*
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* It is a requirement for firmware to have Firmware Interface Table
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* (FIT), which contains pointers to each microcode update.
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* The microcode update is loaded for all logical processors before
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* cpu reset vector.
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*
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* All SoC since Gen-4 has above mechanism in place to load microcode
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* even before hitting CPU reset vector. Hence skipping FSP-T loading
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* microcode after CPU reset by passing '0' value to
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* FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize.
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*
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* Note: CodeRegionSize must be smaller than or equal to 16MiB to not
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* overlap with LAPIC or the CAR area at 0xfef00000.
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*/
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.MicrocodeRegionBase = 0,
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.MicrocodeRegionSize = 0,
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.CodeRegionBase = (uint32_t)0x100000000ULL - CACHE_ROM_SIZE,
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.CodeRegionSize = (uint32_t)CACHE_ROM_SIZE,
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},
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};
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#endif
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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/* Call lib/bootblock.c main */
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