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soc/amd/common/include/gpio_defs.h: Add comment for accuracy 

The GPIO debounce timebase bit 4 is only 183uS on Picasso. On the other
SoCs it is 244uS. This affects the 1mS and 2mS actual debounce times
slightly.

Time  PCO      Others
1mS   0.915mS  1.220mS
2mS   2.013mS  2.684mS

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69209
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Fred Reitberger 2022-11-04 09:16:06 -04:00
parent 502dc54ffc
commit 5e8e911b7c
1 changed files with 1 additions and 0 deletions
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1
src/soc/amd/common/block/include/amdblocks/gpio_defs.h
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@ -113,6 +113,7 @@
#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_REMOVE << DEB_GLITCH_SHIFT)
#define GPIO_TIMEBASE_61uS 0
/* The next value is only 183uS on Picasso. It is 244uS on Cezanne and later SoCs */
#define GPIO_TIMEBASE_183uS (1 << 4)
#define GPIO_TIMEBASE_15560uS (1 << 7)
#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | GPIO_TIMEBASE_15560uS)