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include/cpu/amd/mtrr: rename functions to get top of memory regions 

Rename amd_topmem and amd_topmem2 to get_top_of_mem_below_4gb and
get_top_of_mem_above_4g to make it clearer what those functions return.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6e98d94c731af74aea0ce276a9a7e4867e3986f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit is contained in:
Felix Held 2023-04-20 12:55:55 +02:00
parent df2edde891
commit 5e9afe7272
4 changed files with 6 additions and 6 deletions
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2
src/cpu/amd/mtrr/amd_mtrr.c
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@ -7,7 +7,7 @@
void add_uma_resource_below_tolm(struct device *nb, int idx) void add_uma_resource_below_tolm(struct device *nb, int idx)
{ {
uint32_t topmem = amd_topmem(); uint32_t topmem = get_top_of_mem_below_4gb();
uint32_t top_of_cacheable = restore_top_of_low_cacheable(); uint32_t top_of_cacheable = restore_top_of_low_cacheable();
if (top_of_cacheable == topmem) if (top_of_cacheable == topmem)

4
src/include/cpu/amd/mtrr.h
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@ -65,12 +65,12 @@ static __always_inline void wrmsr_amd(unsigned int index, msr_t msr)
); );
} }
static inline uint64_t amd_topmem(void) static inline uint64_t get_top_of_mem_below_4gb(void)
{ {
return rdmsr(TOP_MEM).lo; return rdmsr(TOP_MEM).lo;
} }
static inline uint64_t amd_topmem2(void) static inline uint64_t get_top_of_mem_above_4g(void)
{ {
msr_t msr = rdmsr(TOP_MEM2); msr_t msr = rdmsr(TOP_MEM2);
return (uint64_t)msr.hi << 32 | msr.lo; return (uint64_t)msr.hi << 32 | msr.lo;

4
src/northbridge/amd/pi/00730F01/northbridge.c
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@ -781,7 +781,7 @@ static void domain_read_resources(struct device *dev)
pci_domain_read_resources(dev); pci_domain_read_resources(dev);
/* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */
mmio_basek = amd_topmem() >> 10; mmio_basek = get_top_of_mem_below_4gb() >> 10;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
/* if the hw mem hole is already set in raminit stage, here we will compare /* if the hw mem hole is already set in raminit stage, here we will compare
@ -837,7 +837,7 @@ static void domain_read_resources(struct device *dev)
sizek = 0; sizek = 0;
} }
else { else {
uint64_t topmem2 = amd_topmem2(); uint64_t topmem2 = get_top_of_mem_above_4g();
basek = 4 * 1024 * 1024; basek = 4 * 1024 * 1024;
sizek = topmem2 / 1024 - basek; sizek = topmem2 / 1024 - basek;
} }

2
src/soc/amd/stoneyridge/northbridge.c
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@ -276,7 +276,7 @@ struct device_operations stoneyridge_northbridge_operations = {
*/ */
void amd_initcpuio(void) void amd_initcpuio(void)
{ {
uintptr_t topmem = amd_topmem(); uintptr_t topmem = get_top_of_mem_below_4gb();
uintptr_t base, limit; uintptr_t base, limit;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ /* Enable legacy video routing: D18F1xF4 VGA Enable */