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soc/amd/common/psp_verstage: Enable Legacy IO only on older SoCs 

With reference to the Picasso PPR 55570 Rev 3.18, LegacyIoEn bit is 0 on
reset and setting it will enable the decoding of the following legacy IO
ports:
0x20, 0x21, 0xA0, 0xA1 (PIC);
0x40, 0x41, 0x42, 0x43, 0x61 (8254 timer);
0x70, 0x71, 0x72, 0x73 (RTC);
0x92.

Verstage does not use those legacy IO ports. Also newer SoCs like
Phoenix do not support Legacy I/O registers to access Power Management
registers and accessing them from PSP verstage causes a hang. Hence
enable legacy IO only on platforms that support it.

BUG=b::284984667
TEST=Build Myst BIOS image with PSP Verstage. Boot to OS successfully
with PSP verstage.

Change-Id: I5e74b4cd1fa7e942770976e5e2197ded47503660
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76692
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2023-07-21 18:05:25 -06:00 committed by Martin L Roth
parent 0154fa57ee
commit 5eb77928e4
1 changed files with 2 additions and 1 deletions
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3
src/soc/amd/common/psp_verstage/psp_verstage.c
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@ -309,7 +309,8 @@ void Main(void)
verstage_mainboard_early_init(); verstage_mainboard_early_init();
svc_write_postcode(POSTCODE_LATE_INIT); svc_write_postcode(POSTCODE_LATE_INIT);
fch_io_enable_legacy_io(); if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS))
fch_io_enable_legacy_io();
printk(BIOS_DEBUG, "calling verstage_soc_spi_init\n"); printk(BIOS_DEBUG, "calling verstage_soc_spi_init\n");
verstage_soc_spi_init(); verstage_soc_spi_init();