sb/intel/i82801gx: Detect if the southbridge supports AHCI
This automatically detects whether the southbridge supports AHCI. If AHCI support is selected it will be used unless "sata_no_ahci" is set in the devicetree to override the behavior. Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -64,7 +64,6 @@ chip northbridge/intel/i945
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register "gpi1_routing" = "2"
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register "gpi7_routing" = "2"
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register "sata_ahci" = "0x1"
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register "sata_ports_implemented" = "0x04"
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register "gpe0_en" = "0x11000006"
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@ -51,7 +51,6 @@ chip northbridge/intel/x4x # Northbridge
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register "gpi13_routing" = "2"
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register "ide_enable_primary" = "0x1"
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register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
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register "sata_ports_implemented" = "0x3"
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register "gpe0_en" = "0x440"
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@ -46,7 +46,6 @@ chip northbridge/intel/x4x # Northbridge
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register "pirqh_routing" = "0x0b"
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register "ide_enable_primary" = "0x1"
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register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
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register "sata_ports_implemented" = "0x3"
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register "gpe0_en" = "0x440"
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@ -44,7 +44,6 @@ chip northbridge/intel/x4x # Northbridge
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register "pirqh_routing" = "0x0b"
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register "ide_enable_primary" = "0x1"
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register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
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register "sata_ports_implemented" = "0x3"
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register "gpe0_en" = "0x440"
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@ -46,7 +46,6 @@ chip northbridge/intel/x4x # Northbridge
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register "pirqh_routing" = "0x0b"
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register "ide_enable_primary" = "0x1"
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register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
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register "gpe0_en" = "0x440"
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device pci 1b.0 on # Audio
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@ -53,7 +53,6 @@ chip northbridge/intel/i945
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register "ide_legacy_combined" = "0x0"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "sata_ahci" = "0x0"
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register "p_cnt_throttling_supported" = "0"
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@ -43,7 +43,6 @@ chip northbridge/intel/x4x # Northbridge
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "ide_enable_primary" = "0x1"
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register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
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register "gpe0_en" = "0x04000440"
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device pci 1b.0 on end # Audio
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@ -40,7 +40,6 @@ chip northbridge/intel/pineview # Northbridge
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register "pirqf_routing" = "0x0b"
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register "pirqg_routing" = "0x0b"
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register "pirqh_routing" = "0x0b"
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register "sata_ahci" = "0x1"
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register "sata_ports_implemented" = "0x3"
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register "gpe0_en" = "0x441"
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@ -47,7 +47,6 @@ chip northbridge/intel/x4x # Northbridge
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register "ide_enable_primary" = "0x0"
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register "ide_enable_secondary" = "0x0"
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register "sata_ahci" = "0x0" # AHCI does not work
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register "sata_ports_implemented" = "0x3"
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device pci 1b.0 on end # Audio
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@ -57,7 +57,6 @@ chip northbridge/intel/i945
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register "ide_legacy_combined" = "0x1"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "sata_ahci" = "0x0"
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register "c3_latency" = "85"
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register "docking_supported" = "1"
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@ -76,7 +76,6 @@ chip northbridge/intel/i945
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register "ide_legacy_combined" = "0x0"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "sata_ahci" = "0x0"
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register "c3_latency" = "85"
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register "p_cnt_throttling_supported" = "0"
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@ -48,7 +48,6 @@ chip northbridge/intel/x4x # Northbridge
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register "ide_legacy_combined" = "0x0" # Combined mode broken
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "sata_ahci" = "0x0" # AHCI does not work
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register "sata_ports_implemented" = "0x3"
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register "gpe0_en" = "0x40"
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@ -36,7 +36,6 @@ chip northbridge/intel/i945
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register "ide_legacy_combined" = "0x0"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "sata_ahci" = "0x1"
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register "c3_latency" = "85"
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register "p_cnt_throttling_supported" = "0"
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@ -38,7 +38,6 @@ chip northbridge/intel/pineview # Northbridge
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register "pirqf_routing" = "0x0b"
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register "pirqg_routing" = "0x0b"
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register "pirqh_routing" = "0x0b"
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register "sata_ahci" = "0x1"
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register "sata_ports_implemented" = "0x3"
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register "gpe0_en" = "0x20000040"
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@ -50,7 +50,6 @@ chip northbridge/intel/i945
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register "ide_legacy_combined" = "0x0"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "sata_ahci" = "0x0"
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register "c3_latency" = "85"
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register "p_cnt_throttling_supported" = "0"
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@ -63,7 +63,6 @@ chip northbridge/intel/x4x # Northbridge
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register "gpi15_routing" = "2"
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register "ide_enable_primary" = "0x1"
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register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
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register "gpe0_en" = "0x440"
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device pci 1b.0 on # Audio
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@ -36,7 +36,6 @@ chip northbridge/intel/i945
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register "ide_legacy_combined" = "0x1"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x1"
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register "sata_ahci" = "0x0"
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register "c3_latency" = "85"
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register "p_cnt_throttling_supported" = "0"
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@ -72,7 +72,6 @@ chip northbridge/intel/i945
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register "gpi12_routing" = "2"
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register "gpi8_routing" = "2"
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register "sata_ahci" = "0x1"
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register "sata_ports_implemented" = "0x01"
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register "gpe0_en" = "0x11000006"
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@ -44,7 +44,6 @@ chip northbridge/intel/x4x # Northbridge
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register "gpi13_routing" = "1" # ??vendor
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register "ide_enable_primary" = "0x1"
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register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
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register "gpe0_en" = "0x440"
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device pci 1b.0 on end # Audio
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@ -65,7 +65,6 @@ chip northbridge/intel/i945
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register "gpi12_routing" = "1"
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register "gpi8_routing" = "2"
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register "sata_ahci" = "0x1"
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register "sata_ports_implemented" = "0x01"
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register "gpe0_en" = "0x11000006"
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@ -71,7 +71,6 @@ chip northbridge/intel/i945
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register "gpi12_routing" = "2"
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register "gpi8_routing" = "2"
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register "sata_ahci" = "0x1"
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register "sata_ports_implemented" = "0x01"
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register "gpe0_en" = "0x11000006"
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@ -61,7 +61,6 @@ chip northbridge/intel/i945
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register "ide_legacy_combined" = "0x1"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "sata_ahci" = "0x0"
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device pci 1b.0 off end # High Definition Audio
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device pci 1c.0 on end # PCIe port 1
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@ -18,6 +18,12 @@
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#include <stdint.h>
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enum sata_mode {
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SATA_MODE_AHCI = 0,
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SATA_MODE_IDE_LEGACY_COMBINED,
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SATA_MODE_IDE_PLAIN,
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};
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struct southbridge_intel_i82801gx_config {
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/**
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* Interrupt Routing configuration
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@ -65,7 +71,7 @@ struct southbridge_intel_i82801gx_config {
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uint32_t ide_legacy_combined;
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uint32_t ide_enable_primary;
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uint32_t ide_enable_secondary;
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uint32_t sata_ahci;
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enum sata_mode sata_mode;
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uint32_t sata_ports_implemented;
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/* Enable linear PCIe Root Port function numbers starting at zero */
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@ -82,6 +82,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
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#define FDVCT 0xe4
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#define PCIE_4_PORTS_MAX (1 << 7)
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#define AHCI_UNSUPPORTED (1 << 3)
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/* GEN_PMCON_3 bits */
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#define RTC_BATTERY_DEAD (1 << 2)
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@ -51,18 +51,42 @@ static u8 get_ich7_sata_ports(void)
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void sata_enable(struct device *dev)
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{
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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struct southbridge_intel_i82801gx_config *config = dev->chip_info;
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if (config->sata_ahci) {
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if (config->sata_mode == SATA_MODE_AHCI) {
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/* Check if the southbridge supports AHCI */
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struct device *lpc_dev = pcidev_on_root(31, 0);
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if (!lpc_dev) {
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/* According to the PCI spec function 0 on a bus:device
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needs to be active for other functions to be enabled.
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Since SATA is on the same bus:device as the LPC
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bridge, it makes little sense to continue. */
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die("Couldn't find the LPC device!\n");
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}
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const bool ahci_supported = !(pci_read_config32(lpc_dev, FDVCT)
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& AHCI_UNSUPPORTED);
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if (!ahci_supported) {
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/* Fallback to IDE PLAIN for sata for the rest of the
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initialization */
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config->sata_mode = SATA_MODE_IDE_PLAIN;
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printk(BIOS_DEBUG,
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"AHCI not supported, falling back to plain mode.\n");
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}
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}
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if (config->sata_mode == SATA_MODE_AHCI) {
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/* Set map to ahci */
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pci_write_config8(dev, SATA_MAP,
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(pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40);
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(pci_read_config8(dev, SATA_MAP)
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& ~0xc3) | 0x40);
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} else {
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/* Set map to ide */
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pci_write_config8(dev, SATA_MAP,
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pci_read_config8(dev, SATA_MAP) & ~0xc3);
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}
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/* At this point, the new pci id will appear on the bus */
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}
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/* Enable BARs */
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pci_write_config16(dev, PCI_COMMAND, 0x0007);
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if (config->ide_legacy_combined) {
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switch (config->sata_mode) {
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case SATA_MODE_IDE_LEGACY_COMBINED:
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printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
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/* No AHCI: clear AHCI base */
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pci_write_config32(dev, 0x24, 0x00000000);
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/* Restrict ports - 0 and 2 only available */
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ports &= 0x5;
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} else if (config->sata_ahci) {
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break;
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case SATA_MODE_AHCI:
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printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
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/* Allow both Legacy and Native mode */
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pci_write_config8(dev, 0x09, 0x8f);
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ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
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ahci_bar[3] = config->sata_ports_implemented;
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} else {
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break;
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default:
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case SATA_MODE_IDE_PLAIN:
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printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
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/* Set Sata Controller Mode. No Mapping(?) */
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pci_write_config8(dev, SATA_MAP, 0x00);
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/* Set IDE I/O Configuration */
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reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
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pci_write_config32(dev, IDE_CONFIG, reg32);
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break;
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}
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/* Set port control */
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