mainboard/google/reef: Bump mainboard mem version

This change is to bump fsp_memory_mainboard_version in order to
trigger MRC full training

BUG=b:119481870
CQ-DEPEND=CL:*716558
BRANCH=reef, coral
TEST=make sure MRC retraining is triggered and the MRC cache is
     updated to newer version.

Change-Id: I92463045f7a808fb25aaa7a2d5f6fcde36dfb458
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/29647
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kane Chen 2018-11-15 17:48:48 +08:00 committed by Furquan Shaikh
parent 8f6af1cc52
commit 5ebcea3aaa
1 changed files with 6 additions and 0 deletions

View File

@ -17,6 +17,7 @@
#include <gpio.h> #include <gpio.h>
#include <soc/meminit.h> #include <soc/meminit.h>
#include <variant/gpio.h> #include <variant/gpio.h>
#include <fsp/api.h>
const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = { const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
/* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
@ -167,3 +168,8 @@ size_t __weak variant_memory_sku(void)
* exist. */ * exist. */
return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
} }
uint8_t fsp_memory_mainboard_version(void)
{
return 1;
}