mb/google/asurada: enable SPI devices
Configure and initialize EC and TPM on Asurada. BUG=none TEST=boot asurada Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46385 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -39,7 +39,7 @@ config MAINBOARD_PART_NUMBER
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config DRIVER_TPM_SPI_BUS
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config DRIVER_TPM_SPI_BUS
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hex
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hex
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default 0x0
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default 0x5
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# On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus.
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# On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus.
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# The number here should be a virtual value as (SPI_BUS_NUMBER + 1).
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# The number here should be a virtual value as (SPI_BUS_NUMBER + 1).
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@ -49,6 +49,6 @@ config BOOT_DEVICE_SPI_FLASH_BUS
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config EC_GOOGLE_CHROMEEC_SPI_BUS
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config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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hex
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default 0x2
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default 0x1
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endif
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endif
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@ -1,7 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <bootblock_common.h>
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#include <soc/spi.h>
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void bootblock_mainboard_init(void)
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void bootblock_mainboard_init(void)
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{
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{
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mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
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mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
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}
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}
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