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mb/google/asurada: enable SPI devices 

Configure and initialize EC and TPM on Asurada.

BUG=none
TEST=boot asurada

Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46385
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nicolas Boichat 2020-05-19 14:24:33 +08:00 committed by Hung-Te Lin
parent aa752158a6
commit 5ed4d63fe1
2 changed files with 5 additions and 2 deletions
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4
src/mainboard/google/asurada/Kconfig
View File

@ -39,7 +39,7 @@ config MAINBOARD_PART_NUMBER
config DRIVER_TPM_SPI_BUS
hex
default 0x0
default 0x5
# On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus.
# The number here should be a virtual value as (SPI_BUS_NUMBER + 1).
@ -49,6 +49,6 @@ config BOOT_DEVICE_SPI_FLASH_BUS
config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 0x2
default 0x1
endif

3
src/mainboard/google/asurada/bootblock.c
View File

@ -1,7 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <soc/spi.h>
void bootblock_mainboard_init(void)
{
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
}