siemens/sitemp_g1p1: Add more devices to PIR and MP table
Linux 2.4 is happier that way Change-Id: I016609ae1e004ec856e8223893352dcdd061b291 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/346 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
parent
481814d1ab
commit
5ed8cc0d62
|
@ -117,6 +117,11 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
/* ide */
|
||||
write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 1, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 1, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
|
|
|
@ -60,6 +60,61 @@ static void *smp_write_config_table(void *v)
|
|||
}
|
||||
mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0);
|
||||
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
|
||||
|
||||
/* usb */
|
||||
PCI_INT(0x0, 0x13, 0x0, 0x10);
|
||||
PCI_INT(0x0, 0x13, 0x1, 0x11);
|
||||
PCI_INT(0x0, 0x13, 0x2, 0x12);
|
||||
PCI_INT(0x0, 0x13, 0x3, 0x13);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x12, 0x1, 0x16);
|
||||
|
||||
/* SMBus/ACPI */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
/* IDE */
|
||||
PCI_INT(0x0, 0x14, 0x1, 0x11);
|
||||
/* HDA */
|
||||
PCI_INT(0x0, 0x14, 0x2, 0x12);
|
||||
/* LPC */
|
||||
PCI_INT(0x0, 0x14, 0x3, 0x13);
|
||||
|
||||
/* GFX ? */
|
||||
PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
|
||||
PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
|
||||
|
||||
/* PCIe slots */
|
||||
PCI_INT(0x2, 0x00, 0x00, 0x10);
|
||||
PCI_INT(0x2, 0x00, 0x01, 0x11);
|
||||
PCI_INT(0x2, 0x00, 0x02, 0x12);
|
||||
PCI_INT(0x2, 0x00, 0x03, 0x13);
|
||||
|
||||
/* PCIe slots */
|
||||
PCI_INT(0x3, 0x00, 0x00, 0x11);
|
||||
PCI_INT(0x3, 0x00, 0x01, 0x12);
|
||||
PCI_INT(0x3, 0x00, 0x02, 0x13);
|
||||
PCI_INT(0x3, 0x00, 0x03, 0x10);
|
||||
|
||||
/* PCIe slots */
|
||||
PCI_INT(0x4, 0x00, 0x00, 0x12);
|
||||
PCI_INT(0x4, 0x00, 0x01, 0x13);
|
||||
PCI_INT(0x4, 0x00, 0x02, 0x10);
|
||||
PCI_INT(0x4, 0x00, 0x03, 0x11);
|
||||
|
||||
/* PCIe slots */
|
||||
PCI_INT(0x5, 0x00, 0x00, 0x13);
|
||||
PCI_INT(0x5, 0x00, 0x01, 0x10);
|
||||
PCI_INT(0x5, 0x00, 0x02, 0x11);
|
||||
PCI_INT(0x5, 0x00, 0x03, 0x12);
|
||||
|
||||
/* onboard NIC ? */
|
||||
PCI_INT(bus_sb600[1], 0x7, 0x0, 0x13);
|
||||
PCI_INT(bus_sb600[1], 0x7, 0x1, 0x10);
|
||||
PCI_INT(bus_sb600[1], 0x7, 0x2, 0x11);
|
||||
PCI_INT(bus_sb600[1], 0x7, 0x3, 0x12);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
mptable_lintsrc(mc, isa_bus);
|
||||
|
||||
|
|
Loading…
Reference in New Issue