inteltool: Support PM registers on Cougar/Panther Point
This adds the power management register definitions for Intel's Cougar
Point and Panther Point platform controller hubs (PCH). The definitions
are actually a subset of the older ICH10R registers: I've added just
those that are mentioned in the public specifications in [1] and [2].
I've tested dumping with an H77 PCH.
NM70 is missing in [1]. Therefore, I didn't add it here.
[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
Document-Number: 324645-006
[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
Datasheet
Document-Number: 326776-003
Change-Id: Ia6945fe96cd96b568ed5191e91dbba5556e1ee95
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2985
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Nico Huber
Stefan Reinauer
parent
82d2d442c0
commit
5ed986b8ab
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@ -21,6 +21,57 @@
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#include <stdio.h>
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#include <stdio.h>
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#include "inteltool.h"
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#include "inteltool.h"
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static const io_register_t pch_pm_registers[] = {
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{ 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
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{ 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
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{ 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK
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{ 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK
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{ 0x0c, 4, "RESERVED" },
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{ 0x10, 4, "RESERVED" },
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{ 0x14, 4, "RESERVED" },
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{ 0x18, 4, "RESERVED" },
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{ 0x1c, 4, "RESERVED" },
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{ 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK
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{ 0x28, 8, "GPE0_EN" }, // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8
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{ 0x30, 4, "SMI_EN" },
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{ 0x34, 4, "SMI_STS" },
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{ 0x38, 2, "ALT_GP_SMI_EN" },
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{ 0x3a, 2, "ALT_GP_SMI_STS" },
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{ 0x3c, 1, "UPRWC" }, // USB Per-Port registers write control
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{ 0x3d, 1, "RESERVED" },
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{ 0x3e, 2, "RESERVED" },
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{ 0x40, 2, "RESERVED" },
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{ 0x42, 1, "GPE_CNTL" },
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{ 0x43, 1, "RESERVED" },
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{ 0x44, 2, "DEVACT_STS" }, // Device Activity Status
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{ 0x46, 2, "RESERVED" },
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{ 0x48, 4, "RESERVED" },
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{ 0x4c, 4, "RESERVED" },
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{ 0x50, 1, "PM2_CNT" },
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{ 0x51, 1, "RESERVED" },
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{ 0x52, 2, "RESERVED" },
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{ 0x54, 4, "RESERVED" },
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{ 0x58, 4, "RESERVED" },
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{ 0x5c, 4, "RESERVED" },
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/* The TCO registers start here. */
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{ 0x60, 2, "TCO_RLD" },
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{ 0x62, 1, "TCO_DAT_IN" },
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{ 0x63, 1, "TCO_DAT_OUT" },
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{ 0x64, 2, "TCO1_STS" },
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{ 0x66, 2, "TCO2_STS" },
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{ 0x68, 2, "TCO1_CNT" },
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{ 0x6a, 2, "TCO2_CNT" },
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{ 0x6c, 2, "TCO_MESSAGE" },
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{ 0x6e, 1, "TCO_WDCNT" },
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{ 0x6f, 1, "RESERVED" },
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{ 0x70, 1, "SW_IRQ_GEN" },
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{ 0x71, 1, "RESERVED" },
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{ 0x72, 2, "TCO_TMR" },
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{ 0x74, 4, "RESERVED" },
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{ 0x78, 4, "RESERVED" },
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{ 0x7c, 4, "RESERVED" },
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};
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static const io_register_t ich10_pm_registers[] = {
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static const io_register_t ich10_pm_registers[] = {
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{ 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
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{ 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
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{ 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
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{ 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
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@ -605,6 +656,39 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
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printf("\n============= PMBASE ============\n\n");
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printf("\n============= PMBASE ============\n\n");
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switch (sb->device_id) {
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_Z68:
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case PCI_DEVICE_ID_INTEL_P67:
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case PCI_DEVICE_ID_INTEL_UM67:
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case PCI_DEVICE_ID_INTEL_HM65:
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case PCI_DEVICE_ID_INTEL_H67:
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case PCI_DEVICE_ID_INTEL_HM67:
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case PCI_DEVICE_ID_INTEL_Q65:
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case PCI_DEVICE_ID_INTEL_QS67:
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case PCI_DEVICE_ID_INTEL_Q67:
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case PCI_DEVICE_ID_INTEL_QM67:
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case PCI_DEVICE_ID_INTEL_B65:
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case PCI_DEVICE_ID_INTEL_C202:
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case PCI_DEVICE_ID_INTEL_C204:
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case PCI_DEVICE_ID_INTEL_C206:
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case PCI_DEVICE_ID_INTEL_H61:
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case PCI_DEVICE_ID_INTEL_Z77:
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case PCI_DEVICE_ID_INTEL_Z75:
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case PCI_DEVICE_ID_INTEL_Q77:
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case PCI_DEVICE_ID_INTEL_Q75:
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case PCI_DEVICE_ID_INTEL_B75:
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case PCI_DEVICE_ID_INTEL_H77:
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case PCI_DEVICE_ID_INTEL_C216:
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case PCI_DEVICE_ID_INTEL_QM77:
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case PCI_DEVICE_ID_INTEL_QS77:
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case PCI_DEVICE_ID_INTEL_HM77:
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case PCI_DEVICE_ID_INTEL_UM77:
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case PCI_DEVICE_ID_INTEL_HM76:
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case PCI_DEVICE_ID_INTEL_HM75:
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case PCI_DEVICE_ID_INTEL_HM70:
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pmbase = pci_read_word(sb, 0x40) & 0xff80;
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pm_registers = pch_pm_registers;
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size = ARRAY_SIZE(pch_pm_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH10R:
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case PCI_DEVICE_ID_INTEL_ICH10R:
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pmbase = pci_read_word(sb, 0x40) & 0xff80;
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pmbase = pci_read_word(sb, 0x40) & 0xff80;
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pm_registers = ich10_pm_registers;
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pm_registers = ich10_pm_registers;
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