Revert "soc/amd/picasso: Reconfigure SPI speeds after FSP-S has run"

This reverts commit d5f1e0f973.

Reason for revert: FSP-S is now fixed to not touch the SPI
configuration registers. Thus, coreboot does not need to reconfigure
SPI after FSP-S has run.

BUG=b:153506142
TEST=Verified that SPI configuration registers look the same before
and after FSP-S has run. em100 works fine without any additional
changes in coreboot to reconfigure SPI.

Change-Id: I4832e62e0331aa39abe0cca7725915262bb2cf83
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/amd/picasso/chip.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <amdblocks/spi.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -165,13 +164,6 @@ static void soc_init(void *chip_info)
 
 	fsp_silicon_init(acpi_is_wakeup_s3());
 
-	/*
-	 * TODO(furquan): Get rid of this once FSP is fixed to not touch SPI
-	 * registers(b/153506142). Currently, FSP-S reconfigures SPI frequency causing em100 to
-	 * stop working. Thus, reconfigure SPI speeds here.
-	 */
-	fch_spi_config_modes();
-
 	data_fabric_set_mmio_np();
 	southbridge_init(chip_info);
 }