pcengines/apu2: Switch away from ROMCC_BOOTBLOCK

Add early SuperIO initialization in bootblock to enable early console.
Also, remove some southbridge-specific initialization that has been
moved to southbridge bootblock initialization in previous patch.

The board obtains few additional timestamps: start of bootblock, end
of bootblock, starting to load romstage and finished loading romstage.

TEST=boot apu2 and launch Debian with Linux kernel 4.14.50

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36915
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/pcengines/apu2/Kconfig

@@ -20,7 +20,6 @@ if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select ROMCC_BOOTBLOCK
 	select CPU_AMD_PI_00730F01
 	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_PI_AVALON

src/mainboard/pcengines/apu2/Makefile.inc

@@ -14,6 +14,8 @@
 # GNU General Public License for more details.
 #
 
+bootblock-y += bootblock.c
+
 romstage-y += BiosCallOuts.c
 romstage-y += OemCustomize.c
 romstage-y += gpio_ftns.c

src/mainboard/pcengines/apu2/bootblock.c

@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <device/pnp_type.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct5104d/nct5104d.h>
+
+#define SIO_PORT 0x2e
+#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
+#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2)
+
+void bootblock_mainboard_early_init(void)
+{
+	hudson_lpc_port80();
+	hudson_clk_output_48Mhz();
+
+	/* COM2 on apu5 is reserved so only COM1 should be supported */
+	if ((CONFIG_UART_FOR_CONSOLE == 1) &&
+		!CONFIG(BOARD_PCENGINES_APU5))
+		nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
+	else if (CONFIG_UART_FOR_CONSOLE == 0)
+		nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
+}

src/mainboard/pcengines/apu2/romstage.c

@@ -14,63 +14,22 @@
  */
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include <device/pci_def.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
-#include <device/pnp.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct5104d/nct5104d.h>
-#include <Fch/Fch.h>
 
 #include "gpio_ftns.h"
 
-#define SIO_PORT 0x2e
-#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
-#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2)
-
 static void early_lpc_init(void);
 
 void board_BeforeAgesa(struct sysinfo *cb)
 {
 	u32 val;
-	pci_devfn_t dev;
-	u32 data;
 
-	/*
-	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
-	 *  LpcClk[1:0]".  This following register setting has been
-	 *  replicated in every reference design since Parmer, so it is
-	 *  believed to be required even though it is not documented in
-	 *  the SoC BKDGs.  Without this setting, there is no serial
-	 *  output.
-	 */
-	outb(0xd2, 0xcd6);
-	outb(0x00, 0xcd7);
-
-	post_code(0x30);
 	early_lpc_init();
 
-	hudson_clk_output_48Mhz();
-	post_code(0x31);
-
-	dev = PCI_DEV(0, 0x14, 3);
-	data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
-	/* enable 0x2e/0x4e IO decoding before configuring SuperIO */
-	pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
-
-	/* COM2 on apu5 is reserved so only COM1 should be supported */
-	if ((CONFIG_UART_FOR_CONSOLE == 1) &&
-		!CONFIG(BOARD_PCENGINES_APU5))
-		nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
-	else if (CONFIG_UART_FOR_CONSOLE == 0)
-		nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
-
-
 	/* Disable SVI2 controller to wait for command completion */
 	val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C);
 	if (!(val & (1 << 30))) {
@@ -78,9 +37,8 @@ void board_BeforeAgesa(struct sysinfo *cb)
 		pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val);
 	}
 
-	/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
+	/* Release GPIO32/33 for other uses. */
-	outb(0xea, 0xcd6);
+	pm_write8(0xea, 1);
-	outb(0x1, 0xcd7);
 }
 
 static void early_lpc_init(void)