device_ops: add device_t argument to acpi_fill_ssdt_generator

`device_t device` is missing as argument. Every device_op function
should have a `device_t device` argument.

Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9598
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/arch/x86/boot/acpi.c

@@ -325,7 +325,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
 		struct device *dev;
 		for (dev = all_devices; dev; dev = dev->next)
 			if (dev->ops && dev->ops->acpi_fill_ssdt_generator) {
-				dev->ops->acpi_fill_ssdt_generator();
+				dev->ops->acpi_fill_ssdt_generator(dev);
 			}
 		current = (unsigned long) acpigen_get_current();
 	}

src/arch/x86/include/arch/acpi.h

@@ -29,6 +29,7 @@
 
 #include <stdint.h>
 #include <rules.h>
+#include <device/device.h>
 
 #define RSDP_SIG		"RSD PTR "  /* RSDT pointer signature */
 #define ACPI_TABLE_CREATOR	"COREBOOT"  /* Must be exactly 8 bytes long! */
@@ -539,7 +540,7 @@ void acpi_create_hpet(acpi_hpet_t *hpet);
 unsigned long acpi_write_hpet(unsigned long start, acpi_rsdp_t *rsdp);
 
 /* cpu/intel/speedstep/acpi.c */
-void generate_cpu_entries(void);
+void generate_cpu_entries(device_t device);
 #endif
 
 void acpi_create_mcfg(acpi_mcfg_t *mcfg);

src/cpu/intel/fsp_model_206ax/acpi.c

@@ -302,7 +302,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	acpigen_pop_len();
 }
 
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
 {
 	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
 	int totalcores = dev_count_cpu();

src/cpu/intel/fsp_model_406dx/acpi.c

@@ -263,7 +263,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	acpigen_pop_len();
 }
 
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
 {
 	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
 	int totalcores = dev_count_cpu();

src/cpu/intel/haswell/acpi.c

@@ -307,7 +307,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	acpigen_pop_len();
 }
 
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
 {
 	int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6;
 	int totalcores = dev_count_cpu();

src/cpu/intel/model_2065x/acpi.c

@@ -299,7 +299,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	acpigen_pop_len();
 }
 
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
 {
 	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
 	int totalcores = dev_count_cpu();

src/cpu/intel/model_206ax/acpi.c

@@ -302,7 +302,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	acpigen_pop_len();
 }
 
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
 {
 	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
 	int totalcores = dev_count_cpu();

src/cpu/intel/speedstep/acpi.c

@@ -117,7 +117,7 @@ static void gen_pstate_entries(const sst_table_t *const pstates,
 /**
  * @brief Generate ACPI entries for Speedstep for each cpu
  */
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
 {
 	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
 	int totalcores = determine_total_number_of_cores();

src/include/device/device.h

@@ -57,7 +57,7 @@ struct device_operations {
 #endif
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 	unsigned long (*write_acpi_tables)(unsigned long start,  struct acpi_rsdp *rsdp);
-	void (*acpi_fill_ssdt_generator)(void);
+	void (*acpi_fill_ssdt_generator)(device_t dev);
 	void (*acpi_inject_dsdt_generator)(device_t dev);
 #endif
 	const struct pci_operations *ops_pci;

src/mainboard/lenovo/x200/mainboard.c

@@ -32,7 +32,7 @@
 #include <ec/lenovo/h8/h8.h>
 #include "drivers/lenovo/lenovo.h"
 
-static void fill_ssdt(void)
+static void fill_ssdt(device_t device)
 {
 	drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0);
 }

src/mainboard/lenovo/x201/mainboard.c

@@ -87,7 +87,7 @@ static void mainboard_init(device_t dev)
 	printk(BIOS_SPEW, "SPI configured\n");
 }
 
-static void fill_ssdt(void)
+static void fill_ssdt(device_t device)
 {
 	drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0);
 }

src/mainboard/lenovo/x60/mainboard.c

@@ -99,7 +99,7 @@ static void mainboard_init(device_t dev)
 	}
 }
 
-static void fill_ssdt(void)
+static void fill_ssdt(device_t device)
 {
 	drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1);
 }

src/mainboard/tyan/s2891/mainboard.c

@@ -6,7 +6,7 @@
 #include <arch/acpigen.h>
 #include <cpu/amd/amdk8_sysconf.h>
 
-static void mainboard_acpi_fill_ssdt_generator(void) {
+static void mainboard_acpi_fill_ssdt_generator(device_t device) {
 	amd_generate_powernow(0, 0, 0);
 }
 

src/mainboard/tyan/s2892/mainboard.c

@@ -6,7 +6,7 @@
 #include <arch/acpigen.h>
 #include <cpu/amd/amdk8_sysconf.h>
 
-static void mainboard_acpi_fill_ssdt_generator(void) {
+static void mainboard_acpi_fill_ssdt_generator(device_t device) {
 	amd_generate_powernow(0, 0, 0);
 }
 

src/mainboard/tyan/s2895/mainboard.c

@@ -8,7 +8,7 @@
 
 extern u16 pm_base;
 
-static void mainboard_acpi_fill_ssdt_generator(void) {
+static void mainboard_acpi_fill_ssdt_generator(device_t device) {
 	amd_generate_powernow(0, 0, 0);
 }
 

src/mainboard/winent/mb6047/mainboard.c

@@ -6,7 +6,7 @@
 #include <arch/acpigen.h>
 #include <cpu/amd/amdk8_sysconf.h>
 
-static void mainboard_acpi_fill_ssdt_generator(void) {
+static void mainboard_acpi_fill_ssdt_generator(device_t device) {
 	amd_generate_powernow(0, 0, 0);
 }
 

src/northbridge/amd/agesa/family12/northbridge.c

@@ -811,7 +811,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 	return (unsigned long)current;
 }
 
-static void northbridge_fill_ssdt_generator(void)
+static void northbridge_fill_ssdt_generator(device_t device)
 {
 	msr_t msr;
 	char pscope[] = "\\_SB.PCI0";

src/northbridge/amd/agesa/family14/northbridge.c

@@ -793,7 +793,7 @@ static void cpu_bus_init(device_t dev)
 
 /* North Bridge Structures */
 
-static void northbridge_fill_ssdt_generator(void)
+static void northbridge_fill_ssdt_generator(device_t device)
 {
 	msr_t msr;
 	char pscope[] = "\\_SB.PCI0";

src/northbridge/amd/agesa/family15/northbridge.c

@@ -502,7 +502,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 	return (unsigned long)current;
 }
 
-static void northbridge_fill_ssdt_generator(void)
+static void northbridge_fill_ssdt_generator(device_t device)
 {
 	msr_t msr;
 	char pscope[] = "\\_SB.PCI0";

src/northbridge/amd/agesa/family15rl/northbridge.c

@@ -477,7 +477,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 	return (unsigned long)current;
 }
 
-static void northbridge_fill_ssdt_generator(void)
+static void northbridge_fill_ssdt_generator(device_t device)
 {
 	msr_t msr;
 	char pscope[] = "\\_SB.PCI0";

src/northbridge/amd/agesa/family15tn/northbridge.c

@@ -477,7 +477,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 	return (unsigned long)current;
 }
 
-static void northbridge_fill_ssdt_generator(void)
+static void northbridge_fill_ssdt_generator(device_t device)
 {
 	msr_t msr;
 	char pscope[] = "\\_SB.PCI0";

src/northbridge/amd/agesa/family16kb/northbridge.c

@@ -477,7 +477,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 	return (unsigned long)current;
 }
 
-static void northbridge_fill_ssdt_generator(void)
+static void northbridge_fill_ssdt_generator(device_t device)
 {
 	msr_t msr;
 	char pscope[] = "\\_SB.PCI0";

src/northbridge/amd/amdfam10/acpi.c

@@ -196,7 +196,7 @@ void update_ssdtx(void *ssdtx, int i)
 
 }
 
-void northbridge_acpi_write_vars(void)
+void northbridge_acpi_write_vars(device_t device)
 {
 	/*
 	 * If more than one physical CPU is installed, northbridge_acpi_write_vars()

src/northbridge/amd/amdfam10/amdfam10.h

@@ -1076,6 +1076,6 @@ struct acpi_rsdp;
 
 unsigned long northbridge_write_acpi_tables(unsigned long start,
 					    struct acpi_rsdp *rsdp);
-void northbridge_acpi_write_vars(void);
+void northbridge_acpi_write_vars(device_t device);
 
 #endif /* AMDFAM10_H */

src/northbridge/amd/amdk8/acpi.c

@@ -277,7 +277,7 @@ static void k8acpi_write_pci_data(int dlen, const char *name, int offset) {
 	acpigen_pop_len();
 }
 
-void k8acpi_write_vars(void)
+void k8acpi_write_vars(device_t device)
 {
 	msr_t msr;
 	char pscope[] = "\\_SB.PCI0";

src/northbridge/amd/amdk8/acpi.h

@@ -21,7 +21,7 @@
 #define AMDK8_ACPI_H
 #include <arch/acpigen.h>
 
-void k8acpi_write_vars(void);
+void k8acpi_write_vars(device_t device);
 unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp);
 
 #endif

src/northbridge/amd/pi/00630F01/northbridge.c

@@ -471,7 +471,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 	return (unsigned long)current;
 }
 
-static void northbridge_fill_ssdt_generator(void)
+static void northbridge_fill_ssdt_generator(device_t device)
 {
 	msr_t msr;
 	char pscope[] = "\\_SB.PCI0";

src/northbridge/amd/pi/00730F01/northbridge.c

@@ -465,7 +465,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 	return (unsigned long)current;
 }
 
-static void northbridge_fill_ssdt_generator(void)
+static void northbridge_fill_ssdt_generator(device_t device)
 {
 	msr_t msr;
 	char pscope[] = "\\_SB.PCI0";

src/northbridge/intel/fsp_rangeley/acpi.c

@@ -65,7 +65,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	return current;
 }
 
-void northbridge_acpi_fill_ssdt_generator(void)
+void northbridge_acpi_fill_ssdt_generator(device_t device)
 {
 	u32 bmbound;
 	char pscope[] = "\\_SB.PCI0";
@@ -74,5 +74,5 @@ void northbridge_acpi_fill_ssdt_generator(void)
 	acpigen_write_scope(pscope);
 	acpigen_write_name_dword("BMBD", bmbound);
 	acpigen_pop_len();
-	generate_cpu_entries();
+	generate_cpu_entries(device);
 }

src/northbridge/intel/fsp_rangeley/northbridge.h

@@ -27,6 +27,9 @@
 /* Everything below this line is ignored in the DSDT */
 #ifndef __ACPI__
 
+#include <rules.h>
+#include <device/device.h>
+
 /* Device 0:0.0 PCI configuration space (Host Bridge) */
 
 /* SideBand B-UNIT */
@@ -72,7 +75,10 @@ void dump_pci_devices(void);
 void dump_spd_registers(void);
 void dump_mem(unsigned start, unsigned end);
 void report_platform_info(void);
-void northbridge_acpi_fill_ssdt_generator(void);
+
+#if ENV_RAMSTAGE
+void northbridge_acpi_fill_ssdt_generator(device_t device);
+#endif
 
 #endif /* #ifndef __ASSEMBLER__ */
 #endif /* #ifndef __ACPI__ */

src/northbridge/intel/fsp_sandybridge/gma.c

@@ -74,7 +74,7 @@ intel_gma_get_controller_info(void)
 	return &chip->gfx;
 }
 
-static void gma_ssdt(void)
+static void gma_ssdt(device_t device)
 {
 	const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
 	if (!gfx) {

src/northbridge/intel/gm45/gma.c

@@ -502,7 +502,7 @@ intel_gma_get_controller_info(void)
 	return &chip->gfx;
 }
 
-static void gma_ssdt(void)
+static void gma_ssdt(device_t device)
 {
 	const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
 	if (!gfx) {

src/northbridge/intel/haswell/gma.c

@@ -498,7 +498,7 @@ intel_gma_get_controller_info(void)
 	return &chip->gfx;
 }
 
-static void gma_ssdt(void)
+static void gma_ssdt(device_t device)
 {
 	const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
 	if (!gfx) {

src/northbridge/intel/i945/gma.c

@@ -499,7 +499,7 @@ intel_gma_get_controller_info(void)
 	return &chip->gfx;
 }
 
-static void gma_ssdt(void)
+static void gma_ssdt(device_t device)
 {
 	const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
 	if (!gfx) {

src/northbridge/intel/nehalem/gma.c

@@ -1082,7 +1082,7 @@ intel_gma_get_controller_info(void)
 	return &chip->gfx;
 }
 
-static void gma_ssdt(void)
+static void gma_ssdt(device_t device)
 {
 	const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
 	if (!gfx) {

src/northbridge/intel/sandybridge/gma.c

@@ -624,7 +624,7 @@ intel_gma_get_controller_info(void)
 	return &chip->gfx;
 }
 
-static void gma_ssdt(void)
+static void gma_ssdt(device_t device)
 {
 	const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
 	if (!gfx) {

src/northbridge/intel/sch/gma.c

@@ -57,7 +57,7 @@ intel_gma_get_controller_info(void)
 	return &chip->gfx;
 }
 
-static void gma_ssdt(void)
+static void gma_ssdt(device_t device)
 {
 	const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
 	if (!gfx) {

src/soc/intel/baytrail/acpi.c

@@ -447,7 +447,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	acpigen_pop_len();
 }
 
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
 {
 	int core;
 	int pcontrol_blk = get_pmbase(), plen = 6;

src/soc/intel/broadwell/acpi.c

@@ -537,7 +537,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	acpigen_pop_len();
 }
 
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
 {
 	int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;
 	int totalcores = dev_count_cpu();

src/soc/intel/fsp_baytrail/acpi.c

@@ -513,7 +513,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	acpigen_pop_len();
 }
 
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
 {
 	int core;
 	int pcontrol_blk = get_pmbase(), plen = 6;

src/southbridge/amd/amd8111/lpc.c

@@ -128,7 +128,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	return current;
 }
 
-static void southbridge_acpi_fill_ssdt_generator(void) {
+static void southbridge_acpi_fill_ssdt_generator(device_t device) {
 #if CONFIG_SET_FIDVID
 	amd_generate_powernow(pm_base + 0x10, 6, 1);
 	acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");

src/southbridge/amd/sb600/lpc.c

@@ -223,7 +223,7 @@ static void sb600_lpc_enable_resources(device_t dev)
 
 extern u16 pm_base;
 
-static void southbridge_acpi_fill_ssdt_generator(void) {
+static void southbridge_acpi_fill_ssdt_generator(device_t device) {
 	amd_generate_powernow(pm_base + 8, 6, 1);
 }
 

src/southbridge/amd/sb700/lpc.c

@@ -267,7 +267,7 @@ static void sb700_lpc_enable_resources(device_t dev)
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 
-static void southbridge_acpi_fill_ssdt_generator(void) {
+static void southbridge_acpi_fill_ssdt_generator(device_t device) {
 	amd_generate_powernow(ACPI_CPU_CONTROL, 6, 1);
 }
 

src/southbridge/intel/bd82x6x/lpc.c

@@ -797,7 +797,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_gpe1_blk.addrh = 0x0;
 }
 
-static void southbridge_fill_ssdt(void)
+static void southbridge_fill_ssdt(device_t device)
 {
 	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 	config_t *chip = dev->chip_info;

src/southbridge/intel/i82371eb/acpi_tables.c

@@ -45,7 +45,7 @@ static int determine_total_number_of_cores(void)
 	return count;
 }
 
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
 {
 	int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6;
 	int numcpus = determine_total_number_of_cores();

src/southbridge/intel/i82371eb/isa.c

@@ -129,10 +129,10 @@ static void sb_read_resources(struct device *dev)
 }
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-static void southbridge_acpi_fill_ssdt_generator(void)
+static void southbridge_acpi_fill_ssdt_generator(device_t device)
 {
 	acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
-	generate_cpu_entries();
+	generate_cpu_entries(device);
 }
 #endif
 

src/southbridge/intel/i82801ix/lpc.c

@@ -562,7 +562,7 @@ static void southbridge_inject_dsdt(device_t dev)
 	}
 }
 
-static void southbridge_fill_ssdt(void)
+static void southbridge_fill_ssdt(device_t device)
 {
 	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 	config_t *chip = dev->chip_info;

src/southbridge/intel/ibexpeak/lpc.c

@@ -784,7 +784,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_gpe1_blk.addrh = 0x0;
 }
 
-static void southbridge_fill_ssdt(void)
+static void southbridge_fill_ssdt(device_t device)
 {
 	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 	config_t *chip = dev->chip_info;

src/southbridge/nvidia/ck804/lpc.c

@@ -313,7 +313,7 @@ static void ck804_lpc_enable_resources(device_t dev)
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 
-static void southbridge_acpi_fill_ssdt_generator(void)
+static void southbridge_acpi_fill_ssdt_generator(device_t device)
 {
 	amd_generate_powernow(0, 0, 0);
 }

src/southbridge/nvidia/mcp55/lpc.c

@@ -283,7 +283,7 @@ static const struct pci_driver lpc_driver __pci_driver = {
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 
-static void southbridge_acpi_fill_ssdt_generator(void)
+static void southbridge_acpi_fill_ssdt_generator(device_t device)
 {
 	amd_generate_powernow(0, 0, 0);
 }

src/southbridge/via/k8t890/traf_ctrl.c

@@ -126,7 +126,7 @@ static void traf_ctrl_enable_k8t890(struct device *dev)
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 
-static void southbridge_acpi_fill_ssdt_generator(void) {
+static void southbridge_acpi_fill_ssdt_generator(device_t dev) {
 	amd_generate_powernow(0, 0, 0);
 	acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
 }