kunimitsu: Enable SMBus device in devicetree
this patch enables SMBus in device tree for kunimitsu board. BRANCH=none BUG=none TEST=built for kunimitsu; booted on kunimitsu fab3 and verified with lspci Original-Change-Id: I3b2b8c202b71c2a0c602169841978ed0c4d8bf8d Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292971 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id20e6cafda8664bd0ae3a5acecdd66c58c220694 Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/11276 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
parent
3657eef829
commit
5eed3a5518
|
@ -140,7 +140,7 @@ chip soc/intel/skylake
|
||||||
end # LPC Interface
|
end # LPC Interface
|
||||||
device pci 1f.2 on end # Power Management Controller
|
device pci 1f.2 on end # Power Management Controller
|
||||||
device pci 1f.3 on end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech)
|
device pci 1f.3 on end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech)
|
||||||
device pci 1f.4 off end # SMBus Controller
|
device pci 1f.4 on end # SMBus Controller
|
||||||
device pci 1f.5 on end # SPI
|
device pci 1f.5 on end # SPI
|
||||||
device pci 1f.6 off end # GbE Controller
|
device pci 1f.6 off end # GbE Controller
|
||||||
end
|
end
|
||||||
|
|
Loading…
Reference in New Issue