sio/ite/it8783ef: New super i/o chip

This will be used by new Roda boards. Four UARTs and PS/2 keyboard and
mouse are exposed to ACPI. Since our boards only use the environment
controller part, most of the usual pnp interfaces are untested.

Change-Id: Ifeb0327ad115759411716f82585ace5ce55b8464
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17287
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Nico Huber 2016-09-30 11:44:13 +02:00 committed by Nico Huber
parent 21707cc29d
commit 5eef7b34c1
7 changed files with 378 additions and 0 deletions

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@ -26,3 +26,4 @@ subdirs-y += it8718f
subdirs-y += it8721f
subdirs-y += it8728f
subdirs-y += it8772f
subdirs-y += it8783ef

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@ -0,0 +1,21 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2016 secunet Security Networks AG
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SUPERIO_ITE_IT8783EF
bool
select SUPERIO_ITE_COMMON_ROMSTAGE
select SUPERIO_ITE_ENV_CTRL
select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG
select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2

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##
## This file is part of the coreboot project.
##
## Copyright (C) 2016 secunet Security Networks AG
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
ramstage-$(CONFIG_SUPERIO_ITE_IT8783EF) += superio.c

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de>
* Copyright (C) 2013, 2016 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Include this file into a mainboard's DSDT _SB device tree and it will
* expose the IT8783E/F SuperIO and some of its functionality.
*
* It allows the change of IO ports, IRQs and DMA settings on logical
* devices, disabling and reenabling logical devices.
*
* LDN State
* 0x0 FDC Not implemented
* 0x1 UARTA Implemented, untested
* 0x2 UARTB Implemented, untested
* 0x3 PP Not implemented
* 0x4 EC Not implemented
* 0x5 KBC Implemented, untested
* 0x6 MOUSE Implemented, untested
* 0x7 GPIO Not implemented
* 0x8 UARTC Implemented, untested
* 0x9 UARTD Implemented, untested
* 0xa UARTE Not implemented
* 0xb UARTF Not implemented
* 0xc CIR Not implemented
*
* Controllable through preprocessor defines:
* SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
* SUPERIO_PNP_BASE I/O address of the first PnP configuration register
* IT8783EF_SHOW_UARTA If defined, UARTA will be exposed.
* IT8783EF_SHOW_UARTB If defined, UARTB will be exposed.
* IT8783EF_SHOW_UARTC If defined, UARTC will be exposed.
* IT8783EF_SHOW_UARTD If defined, UARTD will be exposed.
* IT8783EF_SHOW_KBC If defined, the KBC will be exposed.
* IT8783EF_SHOW_PS2M If defined, PS/2 mouse support will be exposed.
*/
#undef SUPERIO_CHIP_NAME
#define SUPERIO_CHIP_NAME IT8783EF
#include <superio/acpi/pnp.asl>
#define CONFIGURE_CONTROL CCTL
Device(SUPERIO_DEV) {
Name (_HID, EisaId("PNP0A05"))
Name (_STR, Unicode("ITE IT8783E/F Super I/O"))
Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
/* Mutex for accesses to the configuration ports */
Mutex(CRMX, 1)
/* SuperIO configuration ports */
OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
Field (CREG, ByteAcc, NoLock, Preserve)
{
PNP_ADDR_REG, 8,
PNP_DATA_REG, 8
}
IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
{
Offset (0x02),
CONFIGURE_CONTROL, 8, /* Global configure control */
Offset (0x07),
PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
Offset (0x30),
PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
Offset (0x60),
PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
Offset (0x62),
PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
Offset (0x70),
PNP_IRQ0, 8, /* First IRQ */
}
Method (_CRS)
{
/* Announce the used i/o ports to the OS */
Return (ResourceTemplate () {
IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
})
}
#undef PNP_ENTER_MAGIC_1ST
#undef PNP_ENTER_MAGIC_2ND
#undef PNP_ENTER_MAGIC_3RD
#undef PNP_ENTER_MAGIC_4TH
#undef PNP_EXIT_MAGIC_1ST
#define PNP_ENTER_MAGIC_1ST 0x87
#define PNP_ENTER_MAGIC_2ND 0x01
#define PNP_ENTER_MAGIC_3RD 0x55
#if SUPERIO_PNP_BASE == 0x2e
#define PNP_ENTER_MAGIC_4TH 0x55
#else
#define PNP_ENTER_MAGIC_4TH 0xaa
#endif
#define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL
#define PNP_EXIT_SPECIAL_VAL 0x02
#include <superio/acpi/pnp_config.asl>
#ifdef IT8783EF_SHOW_UARTA
#undef SUPERIO_UART_LDN
#undef SUPERIO_UART_DDN
#undef SUPERIO_UART_PM_REG
#undef SUPERIO_UART_PM_VAL
#undef SUPERIO_UART_PM_LDN
#define SUPERIO_UART_LDN 1
#include <superio/acpi/pnp_uart.asl>
#endif
#ifdef IT8783EF_SHOW_UARTB
#undef SUPERIO_UART_LDN
#undef SUPERIO_UART_DDN
#undef SUPERIO_UART_PM_REG
#undef SUPERIO_UART_PM_VAL
#undef SUPERIO_UART_PM_LDN
#define SUPERIO_UART_LDN 2
#include <superio/acpi/pnp_uart.asl>
#endif
#ifdef IT8783EF_SHOW_KBC
#undef SUPERIO_KBC_LDN
#undef SUPERIO_KBC_PS2M
#undef SUPERIO_KBC_PS2LDN
#define SUPERIO_KBC_LDN 5
#ifdef IT8783EF_SHOW_PS2M
#define SUPERIO_KBC_PS2LDN 6
#endif
#include <superio/acpi/pnp_kbc.asl>
#endif
#ifdef IT8783EF_SHOW_UARTC
#undef SUPERIO_UART_LDN
#undef SUPERIO_UART_DDN
#undef SUPERIO_UART_PM_REG
#undef SUPERIO_UART_PM_VAL
#undef SUPERIO_UART_PM_LDN
#define SUPERIO_UART_LDN 8
#include <superio/acpi/pnp_uart.asl>
#endif
#ifdef IT8783EF_SHOW_UARTD
#undef SUPERIO_UART_LDN
#undef SUPERIO_UART_DDN
#undef SUPERIO_UART_PM_REG
#undef SUPERIO_UART_PM_VAL
#undef SUPERIO_UART_PM_LDN
#define SUPERIO_UART_LDN 9
#include <superio/acpi/pnp_uart.asl>
#endif
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SUPERIO_ITE_IT8783EF_CHIP_H
#define SUPERIO_ITE_IT8783EF_CHIP_H
#include <superio/ite/common/env_ctrl_chip.h>
struct superio_ite_it8783ef_config {
struct ite_ec_config ec;
};
#endif /* SUPERIO_ITE_IT8783EF_CHIP_H */

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SUPERIO_ITE_IT8783EF_H
#define SUPERIO_ITE_IT8783EF_H
#define IT8783EF_FDC 0x00 /* Floppy disk controller */
#define IT8783EF_SP1 0x01 /* COM1 */
#define IT8783EF_SP2 0x02 /* COM2 */
#define IT8783EF_PP 0x03 /* Printer port */
#define IT8783EF_EC 0x04 /* Environment controller */
#define IT8783EF_KBCK 0x05 /* Keyboard */
#define IT8783EF_KBCM 0x06 /* Mouse */
#define IT8783EF_GPIO 0x07 /* GPIO */
#define IT8783EF_SP3 0x08 /* COM3 */
#define IT8783EF_SP4 0x09 /* COM4 */
#define IT8783EF_SP5 0x0a /* COM5 */
#define IT8783EF_SP6 0x0b /* COM6 */
#define IT8783EF_CIR 0x0c /* Consumer IR */
#include <arch/io.h>
#include <stdint.h>
#endif /* SUPERIO_ITE_IT8783EF_H */

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
#include <superio/conf_mode.h>
#include <superio/ite/common/env_ctrl.h>
#include "it8783ef.h"
#include "chip.h"
static void it8783ef_init(struct device *const dev)
{
const struct superio_ite_it8783ef_config *conf;
const struct resource *res;
if (!dev->enabled)
return;
switch (dev->path.pnp.device) {
case IT8783EF_EC:
conf = dev->chip_info;
res = find_resource(dev, PNP_IDX_IO0);
if (!conf || !res)
break;
ite_ec_init(res->base, &conf->ec);
break;
case IT8783EF_KBCK:
pc_keyboard_init(NO_AUX_DEVICE);
break;
default:
break;
}
}
static struct device_operations ops = {
.read_resources = pnp_read_resources,
.set_resources = pnp_set_resources,
.enable_resources = pnp_enable_resources,
.enable = pnp_alt_enable,
.init = it8783ef_init,
.ops_pnp_mode = &pnp_conf_mode_870155_aa,
};
static struct pnp_info pnp_dev_info[] = {
/* Floppy Disk Controller */
{ &ops, IT8783EF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1,
{0x0ff8, 0}, },
/* Serial Port 1 */
{ &ops, IT8783EF_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
/* Serial Port 2 */
{ &ops, IT8783EF_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
/* Printer Port */
{ &ops, IT8783EF_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 |
PNP_MSC0,
{0x0ffc, 0}, {0x0ffc, 0}, },
/* Environmental Controller */
{ &ops, IT8783EF_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 |
PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | PNP_MSC4 |
PNP_MSC5 | PNP_MSC6 | PNP_MSC7,
{0x0ff8, 0}, {0x0ff8, 0}, },
/* KBC Keyboard */
{ &ops, IT8783EF_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
{0x0fff, 0}, {0x0fff, 0}, },
/* KBC Mouse */
{ &ops, IT8783EF_KBCM, PNP_IRQ0 | PNP_MSC0, },
/* GPIO */
{ &ops, IT8783EF_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 |
PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 |
PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 |
PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB,
{0x0ffc, 0}, {0x0fff, 0}, {0x0ff8, 0}, },
/* Serial Port 3 */
{ &ops, IT8783EF_SP3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
/* Serial Port 4 */
{ &ops, IT8783EF_SP4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
/* Serial Port 5 */
{ &ops, IT8783EF_SP5, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
/* Serial Port 6 */
{ &ops, IT8783EF_SP6, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
/* Consumer Infrared */
{ &ops, IT8783EF_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_ite_it8783ef_ops = {
CHIP_NAME("ITE IT8783E/F Super I/O")
.enable_dev = enable_dev,
};