Fix the irq_tables
signed-off-by: ronald g. minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -1,8 +1,8 @@
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/* This file was generated by getpir.c, do not modify!
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/* This file was generated by getpir.c, do not modify!
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(but if you do, please run checkpir on it to verify)
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(but if you do, please run checkpir on it to verify)
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Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
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* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
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*
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Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
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* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
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*/
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*/
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#include <arch/pirq_routing.h>
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#include <arch/pirq_routing.h>
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@ -10,24 +10,23 @@
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const struct irq_routing_table intel_irq_routing_table = {
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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PIRQ_VERSION, /* u16 version */
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32+16*5, /* there can be total 5 devices on the bus */
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32+16*6, /* there can be total 6 devices on the bus */
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0, /* Where the interrupt router lies (bus) */
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0x00, /* Where the interrupt router lies (bus) */
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0x88, /* Where the interrupt router lies (dev) */
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(0x01<<3)|0x0, /* Where the interrupt router lies (dev) */
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0x1c20, /* IRQs devoted exclusively to PCI usage */
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0, /* IRQs devoted exclusively to PCI usage */
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0x1106, /* Vendor */
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0x8086, /* Vendor */
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0x8231, /* Device */
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0x7000, /* Device */
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0, /* Crap (miniport) */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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0x7, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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{
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/* 8231 ethernet */
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
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{0x00,(0x01<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0},
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/* 8231 internal */
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{0x00,(0x02<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0},
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{0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
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{0x00,(0x03<<3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0},
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/* PCI slot */
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{0x00,(0x04<<3)|0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0},
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{0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
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{0x00,(0x05<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0},
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{0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
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{0x00,(0x06<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0},
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{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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unsigned long write_pirq_routing_table(unsigned long addr)
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@ -7,6 +7,9 @@ option ROM_SIZE=256*1024
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option CC="gcc -m32"
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option CC="gcc -m32"
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option HAVE_PIRQ_TABLE=1
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option IRQ_SLOT_COUNT=6
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romimage "image"
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romimage "image"
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option ROM_IMAGE_SIZE=0x10000
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option ROM_IMAGE_SIZE=0x10000
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option LINUXBIOS_EXTRA_VERSION="-OpenBIOS"
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option LINUXBIOS_EXTRA_VERSION="-OpenBIOS"
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