mb/pcengines/alixxx: Drop boards
These boards are still using LATE_CBMEM which was agreed upon to be removed after release 4.7. It is now more than 1 year later and they still linger around. The work and review to bring those boards up to date can happen on the 4.9 branch and then squashed and merged back into mainline when done. Change-Id: Iede79ef50681f769a47ce3d66b335dae92aef56b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
250f01e7e3
commit
5ef8e6ebd1
|
|
@ -1,32 +0,0 @@
|
|||
if BOARD_PCENGINES_ALIX1C
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_GEODE_LX
|
||||
select NORTHBRIDGE_AMD_LX
|
||||
select SOUTHBRIDGE_AMD_CS5536
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select HAVE_PIRQ_TABLE
|
||||
select PIRQ_ROUTE
|
||||
select UDELAY_TSC
|
||||
select BOARD_ROMSIZE_KB_512
|
||||
select POWER_BUTTON_DEFAULT_DISABLE
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_CMOS_DEFAULT
|
||||
select NO_EARLY_SMBUS
|
||||
select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
|
||||
select MISSING_BOARD_RESET
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default pcengines/alix1c
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "ALIX.1C"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 5
|
||||
|
||||
endif # BOARD_PCENGINES_ALIX1C
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_PCENGINES_ALIX1C
|
||||
bool "ALIX.1C"
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
Board name: alix1c
|
||||
Board URL: http://pcengines.ch/alix1c.htm
|
||||
Category: half
|
||||
ROM package: PLCC-32
|
||||
ROM protocol: LPC
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
Vendor cooperation score: 4
|
||||
Vendor cooperation page: PC Engines ALIX.1C Vendor Cooperation Score
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
boot_option=Fallback
|
||||
ECC_memory=Disable
|
||||
power_on_after_fail=Disable
|
||||
debug_level=Debug
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
456 1 e 1 ECC_memory
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
||||
|
|
@ -1,84 +0,0 @@
|
|||
chip northbridge/amd/lx
|
||||
device domain 0 on
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
chip southbridge/amd/cs5536
|
||||
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
|
||||
# SIRQ Mode = Active(Quiet) mode. Save power....
|
||||
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
|
||||
# How to get these? Boot linux and do this:
|
||||
# rdmsr 0x51400025
|
||||
register "lpc_serirq_enable" = "0x0000105a"
|
||||
# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
|
||||
register "lpc_serirq_polarity" = "0x0000EFA5"
|
||||
# mode is high 10 bits (determined from code)
|
||||
register "lpc_serirq_mode" = "1"
|
||||
# Don't yet know how to find this.
|
||||
register "enable_gpio_int_route" = "0x0D0C0700"
|
||||
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
|
||||
register "enable_USBP4_device" = "0" #0: host, 1:device
|
||||
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
|
||||
register "com1_enable" = "0"
|
||||
register "com1_address" = "0x3F8"
|
||||
register "com1_irq" = "4"
|
||||
register "com2_enable" = "0"
|
||||
register "com2_address" = "0x2F8"
|
||||
register "com2_irq" = "3"
|
||||
register "unwanted_vpci[0]" = "0" # End of list has a zero
|
||||
device pci f.0 on # ISA Bridge
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off # CIR
|
||||
io 0x60 = 0x100
|
||||
end
|
||||
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||
io 0x60 = 0x220
|
||||
io 0x62 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.8 on end # GPIO2
|
||||
device pnp 2e.9 on end # GPIO3
|
||||
device pnp 2e.a on end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci f.1 on end # Flash controller
|
||||
device pci f.2 on end # IDE controller
|
||||
device pci f.3 on end # Audio
|
||||
device pci f.4 on end # OHCI
|
||||
device pci f.5 on end # EHCI
|
||||
end
|
||||
end
|
||||
|
||||
# APIC cluster is late CPU init.
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/geode_lx
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
/* Platform IRQs */
|
||||
#define PIRQA 11
|
||||
#define PIRQB 10
|
||||
#define PIRQC 11
|
||||
#define PIRQD 9
|
||||
|
||||
/* Map */
|
||||
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
|
||||
|
||||
/* Link */
|
||||
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
|
||||
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
|
||||
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
|
||||
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
|
||||
|
||||
/*
|
||||
* ALIX1.C interrupt wiring.
|
||||
*
|
||||
* Devices are:
|
||||
*
|
||||
* 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
|
||||
* 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
|
||||
* 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
|
||||
* 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01)
|
||||
* 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
|
||||
* 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
|
||||
* 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
|
||||
* 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
|
||||
* 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
|
||||
*
|
||||
* The only devices that interrupt are:
|
||||
*
|
||||
* What Device IRQ PIN PIN WIRED TO
|
||||
* -------------------------------------------------
|
||||
* AES 00:01.2 0a 01 A A
|
||||
* 3VPCI 00:0c.0 0a 01 A A
|
||||
* eth0 00:0d.0 0b 01 A B
|
||||
* mpci 00:0e.0 0a 01 A A
|
||||
* usb 00:0f.3 0b 02 B B
|
||||
* usb 00:0f.4 0b 04 D D
|
||||
* usb 00:0f.5 0b 04 D D
|
||||
*
|
||||
* The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B.
|
||||
*/
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE,
|
||||
PIRQ_VERSION,
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
|
||||
0x00, /* IRQs devoted exclusively to PCI usage */
|
||||
0x100B, /* Vendor */
|
||||
0x002B, /* Device */
|
||||
0, /* Miniport data */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
|
||||
0x00, /* Checksum */
|
||||
{
|
||||
/* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */
|
||||
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
|
||||
/* CPU */
|
||||
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* PCI (slot 1) */
|
||||
{0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x4, 0x0},
|
||||
|
||||
/* On-board ethernet */
|
||||
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* Mini PCI (slot 2) */
|
||||
{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},
|
||||
|
||||
/* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
|
||||
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
|
|
@ -1,148 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <spd.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/lxdef.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <northbridge/amd/lx/raminit.h>
|
||||
#include <northbridge/amd/lx/northbridge.h>
|
||||
#include <southbridge/amd/cs5536/cs5536.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83627hf/w83627hf.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
/* The part is a Hynix hy5du121622ctp-d43.
|
||||
*
|
||||
* HY 5D U 12 16 2 2 C <blank> T <blank> P D43
|
||||
* Hynix
|
||||
* DDR SDRAM (5D)
|
||||
* VDD 2.5 VDDQ 2.5 (U)
|
||||
* 512M 8K REFRESH (12)
|
||||
* x16 (16)
|
||||
* 4banks (2)
|
||||
* SSTL_2 (2)
|
||||
* 4th GEN die (C)
|
||||
* Normal Power Consumption (<blank>)
|
||||
* TSOP (T)
|
||||
* Single Die (<blank>)
|
||||
* Lead Free (P)
|
||||
* DDR400 3-3-3 (D43)
|
||||
*/
|
||||
/* SPD array */
|
||||
static const u8 spdbytes[] = {
|
||||
[SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
|
||||
[SPD_BANK_DENSITY] = 0x40,
|
||||
[SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
|
||||
[SPD_MEMORY_TYPE] = 7,
|
||||
[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
|
||||
[SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
|
||||
[SPD_NUM_BANKS_PER_SDRAM] = 4,
|
||||
[SPD_PRIMARY_SDRAM_WIDTH] = 8,
|
||||
[SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
|
||||
[SPD_NUM_COLUMNS] = 0xa,
|
||||
[SPD_NUM_ROWS] = 3,
|
||||
[SPD_REFRESH] = 0x3a,
|
||||
[SPD_SDRAM_CYCLE_TIME_2ND] = 60,
|
||||
[SPD_SDRAM_CYCLE_TIME_3RD] = 75,
|
||||
[SPD_tRAS] = 40,
|
||||
[SPD_tRCD] = 15,
|
||||
[SPD_tRFC] = 70,
|
||||
[SPD_tRP] = 15,
|
||||
[SPD_tRRD] = 10,
|
||||
};
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address)
|
||||
{
|
||||
printk(BIOS_DEBUG, "spd_read_byte dev %02x", device);
|
||||
|
||||
if (device != DIMM0) {
|
||||
printk(BIOS_DEBUG, " returns 0xff\n");
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, " addr %02x returns %02x\n",
|
||||
address, spdbytes[address]);
|
||||
|
||||
return spdbytes[address];
|
||||
}
|
||||
|
||||
void asmlinkage mainboard_romstage_entry(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{.channel0 = {DIMM0}},
|
||||
};
|
||||
|
||||
SystemPreInit();
|
||||
lx_msr_init();
|
||||
|
||||
cs5536_early_setup();
|
||||
|
||||
/* NOTE: Must do this AFTER cs5536_early_setup()!
|
||||
* It is counting on some early MSR setup for the CS5536.
|
||||
*/
|
||||
cs5536_disable_internal_uart();
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
lx_pll_reset();
|
||||
|
||||
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Switch from Cache as RAM to real RAM.
|
||||
*
|
||||
* There are two ways we could think about this.
|
||||
*
|
||||
* 1. If we are using the romstage.inc ROMCC way, the stack is
|
||||
* going to be re-setup in the code following this code. Just
|
||||
* wbinvd the stack to clear the cache tags. We don't care
|
||||
* where the stack used to be.
|
||||
*
|
||||
* 2. This file is built as a normal .c -> .o and linked in
|
||||
* etc. The stack might be used to return etc. That means we
|
||||
* care about what is in the stack. If we are smart we set
|
||||
* the CAR stack to the same location as the rest of
|
||||
* coreboot. If that is the case we can just do a wbinvd.
|
||||
* The stack will be written into real RAM that is now setup
|
||||
* and we continue like nothing happened. If the stack is
|
||||
* located somewhere other than where LB would like it, you
|
||||
* need to write some code to do a copy from cache to RAM
|
||||
*
|
||||
* We use method 1 on Norwich and on this board too.
|
||||
*/
|
||||
post_code(0x02);
|
||||
printk(BIOS_ERR, "POST 02\n");
|
||||
__asm__("wbinvd\n");
|
||||
printk(BIOS_ERR, "Past wbinvd\n");
|
||||
|
||||
/* We are finding the return does not work on this board. Explicitly
|
||||
* call the label that is after the call to us. This is gross, but
|
||||
* sometimes at this level it is the only way out.
|
||||
*/
|
||||
done_cache_as_ram_main();
|
||||
}
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
if BOARD_PCENGINES_ALIX2C
|
||||
|
||||
# Dummy for abuild
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "ALIX.2C"
|
||||
|
||||
endif
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_PCENGINES_ALIX2C
|
||||
bool "ALIX.2C2 or 2C3"
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
Board name: alix2c
|
||||
Board URL: http://pcengines.ch/alix2c3.htm
|
||||
Category: half
|
||||
ROM package: TSOP-32
|
||||
ROM protocol: LPC
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
if BOARD_PCENGINES_ALIX2C || BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_AMD_GEODE_LX
|
||||
select NORTHBRIDGE_AMD_LX
|
||||
select SOUTHBRIDGE_AMD_CS5536
|
||||
select HAVE_PIRQ_TABLE
|
||||
select PIRQ_ROUTE
|
||||
select UDELAY_TSC
|
||||
select BOARD_ROMSIZE_KB_512
|
||||
select POWER_BUTTON_FORCE_DISABLE
|
||||
select NO_EARLY_SMBUS
|
||||
select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
|
||||
select MISSING_BOARD_RESET
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default pcengines/alix2d
|
||||
|
||||
if BOARD_PCENGINES_ALIX2D
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "ALIX.2D"
|
||||
|
||||
endif
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 7
|
||||
|
||||
endif # BOARD_PCENGINES_ALIX2C || BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_PCENGINES_ALIX2D
|
||||
bool "ALIX.2D2 or 2D3"
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
Board name: alix2d
|
||||
Board URL: http://pcengines.ch/alix2d0.htm
|
||||
Category: half
|
||||
ROM package: TSOP-32
|
||||
ROM protocol: LPC
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
456 1 e 1 ECC_memory
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
chip northbridge/amd/lx
|
||||
device domain 0 on
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
chip southbridge/amd/cs5536
|
||||
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
|
||||
# SIRQ Mode = Active(Quiet) mode. Save power....
|
||||
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
|
||||
# How to get these? Boot linux and do this:
|
||||
# rdmsr 0x51400025
|
||||
register "lpc_serirq_enable" = "0x00001002"
|
||||
# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
|
||||
register "lpc_serirq_polarity" = "0x0000EFFD"
|
||||
# mode is high 10 bits (determined from code)
|
||||
register "lpc_serirq_mode" = "1"
|
||||
# Don't yet know how to find this.
|
||||
register "enable_gpio_int_route" = "0x0D0C0700"
|
||||
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
|
||||
register "enable_USBP4_device" = "0" #0: host, 1:device
|
||||
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
|
||||
register "com1_enable" = "1"
|
||||
register "com1_address" = "0x3F8"
|
||||
register "com1_irq" = "4"
|
||||
register "com2_enable" = "1" # Wired on Alix.2D13 only
|
||||
register "com2_address" = "0x2F8"
|
||||
register "com2_irq" = "3"
|
||||
register "unwanted_vpci[0]" = "0x80000900" # Disable VGA controller (not wired)
|
||||
register "unwanted_vpci[1]" = "0x80007B00" # Disable AC97 controller (not wired)
|
||||
register "unwanted_vpci[2]" = "0" # End of list has a zero
|
||||
device pci f.0 on end # ISA Bridge
|
||||
device pci f.1 on end # Flash controller
|
||||
device pci f.2 on end # IDE controller
|
||||
device pci f.4 on end # OHCI
|
||||
device pci f.5 on end # EHCI
|
||||
end
|
||||
end
|
||||
|
||||
# APIC cluster is late CPU init.
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/geode_lx
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <arch/io.h>
|
||||
#include <southbridge/amd/cs5536/cs5536.h>
|
||||
|
||||
/* Platform IRQs */
|
||||
#define PIRQA 11
|
||||
#define PIRQB 10
|
||||
#define PIRQC 11
|
||||
#define PIRQD 9
|
||||
|
||||
/* Map */
|
||||
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
|
||||
|
||||
/* Link */
|
||||
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
|
||||
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
|
||||
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
|
||||
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
|
||||
|
||||
/*
|
||||
* ALIX.2D3 interrupt wiring.
|
||||
*
|
||||
* Devices are:
|
||||
* 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33)
|
||||
* 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082]
|
||||
* 00:09.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
|
||||
* 00:0a.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
|
||||
* 00:0b.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
|
||||
* 00:0f.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03)
|
||||
* 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01)
|
||||
* 00:0f.4 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02)
|
||||
* 00:0f.5 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02)
|
||||
|
||||
* The only devices that interrupt are:
|
||||
*
|
||||
* What Device IRQ PIN PIN WIRED TO
|
||||
* -------------------------------------------------
|
||||
* AES 00:01.2 0a 01 A A
|
||||
* eth0 00:09.0 0b 01 A B
|
||||
* eth1 00:0a.0 0b 01 A C
|
||||
* eth2 00:0b.0 0b 01 A D
|
||||
* mpci 00:0c.0 0a 01 A A
|
||||
* mpci 00:0c.0 0b 02 B B
|
||||
* usb 00:0f.4 0b 04 D D
|
||||
* usb 00:0f.5 0b 04 D D
|
||||
*
|
||||
* The only swizzled interrupts are the ethernet controllers, where INTA is wired to
|
||||
* interrupt controller lines B, C and D.
|
||||
*/
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE,
|
||||
PIRQ_VERSION,
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
|
||||
0x00, /* IRQs devoted exclusively to PCI usage */
|
||||
0x100B, /* Vendor */
|
||||
0x002B, /* Device */
|
||||
0, /* Miniport data */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
|
||||
0x00, /* Checksum */
|
||||
{
|
||||
/* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */
|
||||
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
|
||||
/* CPU */
|
||||
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* On-board ethernet (Left) */
|
||||
{0x00, (0x09 << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* On-board ethernet (Middle, ALIX.2D3 only) */
|
||||
{0x00, (0x0A << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* On-board ethernet (Right) */
|
||||
{0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* Mini PCI (slot 1) */
|
||||
{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* Mini PCI (slot 2, ALIX.2D2 only) */
|
||||
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
|
||||
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
|
|
@ -1,171 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <spd.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/lxdef.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <southbridge/amd/cs5536/cs5536.h>
|
||||
#include <northbridge/amd/lx/raminit.h>
|
||||
#include <northbridge/amd/lx/northbridge.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
/* The part is a Hynix hy5du121622ctp-d43.
|
||||
*
|
||||
* HY 5D U 12 16 2 2 C <blank> T <blank> P D43
|
||||
* Hynix
|
||||
* DDR SDRAM (5D)
|
||||
* VDD 2.5 VDDQ 2.5 (U)
|
||||
* 512M 8K REFRESH (12)
|
||||
* x16 (16)
|
||||
* 4banks (2)
|
||||
* SSTL_2 (2)
|
||||
* 4th GEN die (C)
|
||||
* Normal Power Consumption (<blank>)
|
||||
* TSOP (T)
|
||||
* Single Die (<blank>)
|
||||
* Lead Free (P)
|
||||
* DDR400 3-3-3 (D43)
|
||||
*/
|
||||
/* SPD array */
|
||||
static const u8 spdbytes[] = {
|
||||
[SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
|
||||
[SPD_BANK_DENSITY] = 0x40,
|
||||
[SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
|
||||
[SPD_MEMORY_TYPE] = 7,
|
||||
[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
|
||||
[SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
|
||||
[SPD_NUM_BANKS_PER_SDRAM] = 4,
|
||||
[SPD_PRIMARY_SDRAM_WIDTH] = 8,
|
||||
[SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
|
||||
[SPD_NUM_COLUMNS] = 0xa,
|
||||
[SPD_NUM_ROWS] = 3,
|
||||
[SPD_REFRESH] = 0x3a,
|
||||
[SPD_SDRAM_CYCLE_TIME_2ND] = 60,
|
||||
[SPD_SDRAM_CYCLE_TIME_3RD] = 75,
|
||||
[SPD_tRAS] = 40,
|
||||
[SPD_tRCD] = 15,
|
||||
[SPD_tRFC] = 70,
|
||||
[SPD_tRP] = 15,
|
||||
[SPD_tRRD] = 10,
|
||||
};
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address)
|
||||
{
|
||||
printk(BIOS_DEBUG, "spd_read_byte dev %02x", device);
|
||||
|
||||
if (device != DIMM0) {
|
||||
printk(BIOS_DEBUG, " returns 0xff\n");
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, " addr %02x returns %02x\n",
|
||||
address, spdbytes[address]);
|
||||
|
||||
return spdbytes[address];
|
||||
}
|
||||
|
||||
/** Early mainboard specific GPIO setup. */
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/*
|
||||
* Enable LEDs GPIO outputs to light up the leds
|
||||
* This is how the original tinyBIOS sets them after boot.
|
||||
* Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it
|
||||
* may be used here, but not after PCI Init.
|
||||
* Note: Prior to a certain release, Linux used a hardwired 0x6100 in the
|
||||
* leds-alix2.c driver. coreboot dynamically assigns this space,
|
||||
* so the driver does not work anymore.
|
||||
* Good workaround: use the newer driver
|
||||
* Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100
|
||||
* This resets the GPIO I/O space to 0x6100.
|
||||
* This may break other things, though.
|
||||
*/
|
||||
outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
|
||||
outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
|
||||
outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
|
||||
|
||||
/* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */
|
||||
outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */
|
||||
outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */
|
||||
}
|
||||
|
||||
void asmlinkage mainboard_romstage_entry(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{.channel0 = {DIMM0}},
|
||||
};
|
||||
|
||||
SystemPreInit();
|
||||
lx_msr_init();
|
||||
|
||||
cs5536_early_setup();
|
||||
|
||||
/* NOTE: Must do this AFTER cs5536_early_setup()!
|
||||
* It is counting on some early MSR setup for the CS5536.
|
||||
*/
|
||||
cs5536_setup_onchipuart(1);
|
||||
mb_gpio_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
lx_pll_reset();
|
||||
|
||||
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Switch from Cache as RAM to real RAM.
|
||||
*
|
||||
* There are two ways we could think about this.
|
||||
*
|
||||
* 1. If we are using the romstage.inc ROMCC way, the stack is
|
||||
* going to be re-setup in the code following this code. Just
|
||||
* wbinvd the stack to clear the cache tags. We don't care
|
||||
* where the stack used to be.
|
||||
*
|
||||
* 2. This file is built as a normal .c -> .o and linked in
|
||||
* etc. The stack might be used to return etc. That means we
|
||||
* care about what is in the stack. If we are smart we set
|
||||
* the CAR stack to the same location as the rest of
|
||||
* coreboot. If that is the case we can just do a wbinvd.
|
||||
* The stack will be written into real RAM that is now setup
|
||||
* and we continue like nothing happened. If the stack is
|
||||
* located somewhere other than where LB would like it, you
|
||||
* need to write some code to do a copy from cache to RAM
|
||||
*
|
||||
* We use method 1 on Norwich and on this board too.
|
||||
*/
|
||||
post_code(0x02);
|
||||
printk(BIOS_ERR, "POST 02\n");
|
||||
__asm__("wbinvd\n");
|
||||
printk(BIOS_ERR, "Past wbinvd\n");
|
||||
|
||||
/* We are finding the return does not work on this board. Explicitly
|
||||
* call the label that is after the call to us. This is gross, but
|
||||
* sometimes at this level it is the only way out.
|
||||
*/
|
||||
done_cache_as_ram_main();
|
||||
}
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
if BOARD_PCENGINES_ALIX6
|
||||
|
||||
# Dummy for abuild
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "ALIX.6"
|
||||
|
||||
endif
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_PCENGINES_ALIX6
|
||||
bool "ALIX.6"
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
Board name: alix6f
|
||||
Board URL: http://pcengines.ch/alix6f2.htm
|
||||
Category: half
|
||||
ROM package: TSOP-32
|
||||
ROM protocol: LPC
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
Loading…
Reference in New Issue