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Documentation: soc/amd/psp: Use real table markup 

Currently, tables on this page are formatted as code blocks with
ASCII tables. Make it real beautiful tables.

Change-Id: I3c46477352b8151f3b0fb0616f909531a0a15c34
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
This commit is contained in:
Evgeny Zinoviev 2020-02-18 14:59:08 +03:00 committed by Patrick Georgi
parent abe9673774
commit 5efe122b27
1 changed files with 136 additions and 129 deletions
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83
Documentation/soc/amd/psp_integration.md
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@ -37,38 +37,40 @@ any of the eligible locations. Below are typical definitions within the
structure (for all families combined). Individual features supported vary by structure (for all families combined). Individual features supported vary by
family and model. family and model.
```eval_rst
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose |
+--------------+---------------+------------------+----------------------------+ +==============+===============+==================+============================+
| Signature | 0x00 | 4 | 0x55aa55aa | | Signature | 0x00 | 4 | 0x55aa55aa |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| IMC FW | 0x04 | 4 | Integrated Micro | | IMC FW | 0x04 | 4 | Integrated Micro |
| | | | Controller: unsupported | | | | | Controller: unsupported |
| | | | but functional in some | | | | | but functional in some |
| | | | systems | | | | | systems |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| GbE FW | 0x08 | 4 | Gigabit Ethernet | | GbE FW | 0x08 | 4 | Gigabit Ethernet |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| xHCI FW | 0x0c | 4 | xHCI firmware | | xHCI FW | 0x0c | 4 | xHCI firmware |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| PSP Dir Tbl | 0x10 | 4 | Pointer to PSP Directory | | PSP Dir Tbl | 0x10 | 4 | Pointer to PSP Directory |
| | | | Table (early devices) | | | | | Table (early devices) |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| PSP Dir Tbl | 0x14 | 4 | Pointer to PSP Directory | | PSP Dir Tbl | 0x14 | 4 | Pointer to PSP Directory |
| | | | Table (later devices and | | | | | Table (later devices and |
| | | | is combo capable) | | | | | is combo capable) |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| BIOS Dir Tbl | 0x18 | 4 | Pointer to BIOS Directory | | BIOS Dir Tbl | 0x18 | 4 | Pointer to BIOS Directory |
| | | | Table for models n* | | | | | Table for models n* |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| BIOS Dir Tbl | 0x1c | 4 | Pointer to BIOS Directory | | BIOS Dir Tbl | 0x1c | 4 | Pointer to BIOS Directory |
| | | | Table for models nn | | | | | Table for models nn |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| BIOS Dir Tbl | 0x20 | 4 | Pointer to BIOS Directory | | BIOS Dir Tbl | 0x20 | 4 | Pointer to BIOS Directory |
| | | | Table for models nnn | | | | | Table for models nnn |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| … | | | ... | | … | | | ... |
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
```
* The Embedded Firmware Structure may support pointers to multiple generations * The Embedded Firmware Structure may support pointers to multiple generations
of devices, e.g. Family 17h Models 00h-0Fh, Family 17h Models 10h-1Fh, etc. of devices, e.g. Family 17h Models 00h-0Fh, Family 17h Models 10h-1Fh, etc.
@ -83,37 +85,38 @@ allowing secondary tables to be referenced by device ID. No coreboot
implementations currently use combo tables. implementations currently use combo tables.
### PSP Directory Table Header ### PSP Directory Table Header
```eval_rst
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose |
+--------------+---------------+------------------+----------------------------+ +==============+===============+==================+============================+
| PSP Cookie | 0x00 | 4 | PSP cookie "$PSP" to | | PSP Cookie | 0x00 | 4 | PSP cookie "$PSP" to |
| | | | recognize the header. | | | | | recognize the header. |
| | | | Cookie “$PL2” for level 2 | | | | | Cookie “$PL2” for level 2 |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Checksum | 0x04 | 4 | 32-bit CRC value of header | | Checksum | 0x04 | 4 | 32-bit CRC value of header |
| | | | below this field and | | | | | below this field and |
| | | | including all entries | | | | | including all entries |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Total Entries| 0x08 | 4 | Number of PSP Directory | | Total Entries| 0x08 | 4 | Number of PSP Directory |
| | | | entries in the table | | | | | entries in the table |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Reserved | 0x0C | 4 | Reserved - Set to zero | | Reserved | 0x0C | 4 | Reserved - Set to zero |
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
```
### PSP Directory Table Entries ### PSP Directory Table Entries
```eval_rst
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | | Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose |
+--------------+---------------+------------------+----------------------------+ +==============+===============+==================+============================+
| Type | 0x00 | 8 | Entry type (see below) | | Type | 0x00 | 8 | Entry type (see below) |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Sub Program | 0x01 | 8 | Specifies sub program | | Sub Program | 0x01 | 8 | Specifies sub program |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Reserved | 0x02 | 16 | Reserved - set to 0 | | Reserved | 0x02 | 16 | Reserved - set to 0 |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Size | 0x04 | 32 | Size of PSP entry in bytes | | Size | 0x04 | 32 | Size of PSP entry in bytes |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Location / | 0x08 | 64 | Location: Physical Address | | Location / | 0x08 | 64 | Location: Physical Address |
| Value | | | of SPIROM location where | | Value | | | of SPIROM location where |
| | | | corresponding PSP entry | | | | | corresponding PSP entry |
@ -122,7 +125,7 @@ implementations currently use combo tables.
| | | | Value: 64-bit value for the| | | | | Value: 64-bit value for the|
| | | | PSP Entry | | | | | PSP Entry |
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
```
### PSP Directory Table Types ### PSP Directory Table Types
**0x00**: AMD public key **0x00**: AMD public key
@ -248,68 +251,72 @@ The BIOS Directory table structure is slightly different from the PSP Directory:
### BIOS Directory Table Header ### BIOS Directory Table Header
```eval_rst
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose |
+--------------+---------------+------------------+----------------------------+ +==============+===============+==================+============================+
| BIOS Cookie | 0x00 | 4 | BIOS cookie "$BHD" to | | BIOS Cookie | 0x00 | 4 | BIOS cookie "$BHD" to |
| | | | recognize the header. | | | | | recognize the header. |
| | | | Cookie “$BL2” for level 2 | | | | | Cookie “$BL2” for level 2 |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Checksum | 0x04 | 4 | 32 bit CRC value of header | | Checksum | 0x04 | 4 | 32 bit CRC value of header |
| | | | below this field and | | | | | below this field and |
| | | | including all entries | | | | | including all entries |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Total Entries| 0x08 | 4 | Number of BIOS Directory | | Total Entries| 0x08 | 4 | Number of BIOS Directory |
| | | | entries in the table | | | | | entries in the table |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Reserved | 0x0C | 4 | Reserved - Set to zero | | Reserved | 0x0C | 4 | Reserved - Set to zero |
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
```
### BIOS Directory Table Entries ### BIOS Directory Table Entries
```eval_rst
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | | Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose |
+--------------+---------------+------------------+----------------------------+ +==============+===============+==================+============================+
| Type | 0x00 | 8 | Entry type (see below) | | Type | 0x00 | 8 | Entry type (see below) |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Region Type | 0x01 | 8 | Setup the memory region's | | Region Type | 0x01 | 8 | Setup the memory region's |
| | | | security attribute for the | | | | | security attribute for the |
| | | | BIOS entry | | | | | BIOS entry |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Reset Image | 0x02[0] | 1 | Boolean value to define the| | Reset Image | 0x02[0] | 1 | Boolean value to define the|
| | | | BIOS entry is a reset | | | | | BIOS entry is a reset |
| | | | binary image | | | | | binary image |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Copy Image | 0x02[1] | 1 | Define the binary image of | | Copy Image | 0x02[1] | 1 | Define the binary image of |
| | | | the BIOS entry is for | | | | | the BIOS entry is for |
| | | | copying over to the memory | | | | | copying over to the memory |
| | | | region | | | | | region |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Read Only | 0x02[2] | 1 | Setup the memory region for| | Read Only | 0x02[2] | 1 | Setup the memory region for|
| | | | the BIOS entry to read only| | | | | the BIOS entry to read only|
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Compressed | 0x02[3] | 1 | Compressed using zlib | | Compressed | 0x02[3] | 1 | Compressed using zlib |
| | | | | | | | | |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Instance | 0x02[7:4] | 4 | Specify the Instance of an | | Instance | 0x02[7:4] | 4 | Specify the Instance of an |
| | | | entry | | | | | entry |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| SubProgram | 0x03[2:0] | 3 | Specify the SubProgram | | SubProgram | 0x03[2:0] | 3 | Specify the SubProgram |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Reserved | 0x03[7:3] | 5 | Reserved - Set to zero | | Reserved | 0x03[7:3] | 5 | Reserved - Set to zero |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Size | 0x04 | 32 | Memory Region Size | | Size | 0x04 | 32 | Memory Region Size |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Source | 0x08 | 64 | Physical Address of SPIROM | | Source | 0x08 | 64 | Physical Address of SPIROM |
| Address | | | location where the data for| | Address | | | location where the data for|
| | | | the corresponding entry is | | | | | the corresponding entry is |
| | | | located | | | | | located |
|--------------|---------------|------------------|----------------------------| +--------------+---------------+------------------+----------------------------+
| Destination | 0x10 | 64 | Destination Address of | | Destination | 0x10 | 64 | Destination Address of |
| Address | | | memory location where the | | Address | | | memory location where the |
| | | | data for the corresponding | | | | | data for the corresponding |
| | | | BIOS Entry is copied | | | | | BIOS Entry is copied |
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
```
### BIOS Directory Table Entry Types ### BIOS Directory Table Entry Types