diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 5827c84d3c..1c37cc3616 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -58,4 +58,16 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff60040
 
+config HAVE_CPU_MICROCODE_FILE
+	bool "Add microcode file"
+	help
+	  The microcode binary
+
+config CPU_MICROCODE_FILE
+	  string "Path and filename of CPU microcode"
+	  default "microcode.bin"
+	  depends on HAVE_CPU_MICROCODE_FILE
+	  help
+	    The path and filename of the file containing the CPU microcode.
+
 endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 7e18f1ba1e..91c7d96aa4 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -18,6 +18,10 @@ subdirs-y += ../../x86/name
 
 ramstage-y += acpi.c
 
+ifeq ($(CONFIG_HAVE_CPU_MICROCODE_FILE), y)
+cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
+endif
+
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
 # We don't have microcode for this CPU
 # Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c
index ab9bcffaee..edbbe1b362 100644
--- a/src/cpu/intel/fsp_model_406dx/bootblock.c
+++ b/src/cpu/intel/fsp_model_406dx/bootblock.c
@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <cpu/x86/cache.h>
+#include <cpu/intel/microcode/microcode.c>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
@@ -86,6 +87,10 @@ static void bootblock_cpu_init(void)
 {
 	/* Check for Warm Reset */
 	check_for_warm_reset();
+
+	/* Load microcode before any caching. */
+	intel_update_microcode_from_cbfs();
+
 	enable_rom_caching();
 	set_no_evict_mode_msr();
 }