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skylake: Check for power failure when WAK_STS is not set 

The PCH does not set PM1_STS[WAK_STS] bit when waking from a
G3 state, which is triggered by hibernate now on chell when we
do a PMIC shutdown.  This means the checks for S5 wake are not
done and instead it is logged as a wake from S0.

BUG=chrome-os-partner:50076
BRANCH=glados
TEST=pass firmware_EventLog test on chell

Change-Id: I3ca05a4824df3401150a63d4b6555f759de40087
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de6c9bac447edd06568193f990f1f4e278576783
Original-Change-Id: I4472498468d620fe69f2b68710e818a4ad287382
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326888
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13696
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Duncan Laurie 2016-02-09 09:21:41 -08:00 committed by Patrick Georgi
parent 3054c8b754
commit 5f0cd58e0e
1 changed files with 8 additions and 0 deletions
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8
src/soc/intel/skylake/romstage/power_state.c
View File

@ -69,6 +69,14 @@ static uint32_t prev_sleep_state(struct chipset_power_state *ps)
} }
/* Clear SLP_TYP. */ /* Clear SLP_TYP. */
outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
} else {
/*
* Check for any power failure to determine if this a wake from
* S5 because the PCH does not set the WAK_STS bit when waking
* from a true G3 state.
*/
if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
prev_sleep_state = SLEEP_STATE_S5;
} }
/* /*