soc/intel/tigerlake: Replace SOC_INTEL_TIGERLAKE_S3 with D3COLD_SUPPORT
The Kconfig option SOC_INTEL_TIGERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Remove it, and instead use D3COLD_SUPPORT so it's clear what the option is doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74405 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -48,7 +48,6 @@ config BOARD_STARLABS_STARBOOK_TGL
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select SOC_INTEL_COMMON_BLOCK_TCSS
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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select SOC_INTEL_TIGERLAKE
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select SOC_INTEL_TIGERLAKE_S3
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select SPI_FLASH_WINBOND
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select TPM_MEASURED_BOOT
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@ -208,12 +208,6 @@ config SOC_INTEL_I2C_DEV_MAX
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int
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default 6
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config SOC_INTEL_TIGERLAKE_S3
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bool
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default n
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help
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Select if using S3 instead of S0ix to disable D3Cold
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config SOC_INTEL_UART_DEV_MAX
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int
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default 3
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@ -676,7 +676,7 @@ Scope (\_SB.PCI0)
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}
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}
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#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
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#if CONFIG(D3COLD_SUPPORT)
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Method (TCON, 0)
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{
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/* Reset IOM D3 cold bit if it is in D3 cold now. */
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@ -787,7 +787,7 @@ Scope (\_SB.PCI0)
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STAT = 0
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}
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}
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#endif // SOC_INTEL_TIGERLAKE_S3
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#endif // D3COLD_SUPPORT
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/*
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* TCSS xHCI device
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@ -27,11 +27,11 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
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Method (_S0W, 0x0)
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{
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#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
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#if CONFIG(D3COLD_SUPPORT)
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Return (0x04)
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#else
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Return (0x03)
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#endif // SOC_INTEL_TIGERLAKE_S3
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#endif // D3COLD_SUPPORT
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}
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/*
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@ -40,7 +40,7 @@ Method (_S0W, 0x0)
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*/
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Method (_PR0)
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{
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#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
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#if CONFIG(D3COLD_SUPPORT)
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If (DUID == 0) {
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Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
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} Else {
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@ -52,12 +52,12 @@ Method (_PR0)
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} Else {
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Return (Package() { \_SB.PCI0.TBT1 })
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}
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#endif // SOC_INTEL_TIGERLAKE_S3
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#endif // D3COLD_SUPPORT
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}
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Method (_PR3)
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{
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#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
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#if CONFIG(D3COLD_SUPPORT)
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If (DUID == 0) {
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Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
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} Else {
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@ -69,7 +69,7 @@ Method (_PR3)
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} Else {
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Return (Package() { \_SB.PCI0.TBT1 })
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}
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#endif // SOC_INTEL_TIGERLAKE_S3
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#endif // D3COLD_SUPPORT
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}
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/*
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@ -247,16 +247,16 @@ Method (_PS3, 0, Serialized)
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Method (_S0W, 0x0, NotSerialized)
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{
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#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
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#if CONFIG(D3COLD_SUPPORT)
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Return (0x4)
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#else
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Return (0x3)
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#endif // SOC_INTEL_ALDERLAKE_S3
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#endif // D3COLD_SUPPORT
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}
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Method (_PR0)
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{
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#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
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#if CONFIG(D3COLD_SUPPORT)
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If ((TUID == 0) || (TUID == 1)) {
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Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
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} Else {
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@ -268,12 +268,12 @@ Method (_PR0)
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} Else {
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Return (Package() { \_SB.PCI0.TBT1 })
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}
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#endif // SOC_INTEL_TIGERLAKE_S3
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#endif // D3COLD_SUPPORT
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}
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Method (_PR3)
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{
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#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
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#if CONFIG(D3COLD_SUPPORT)
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If ((TUID == 0) || (TUID == 1)) {
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Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
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} Else {
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@ -285,7 +285,7 @@ Method (_PR3)
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} Else {
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Return (Package() { \_SB.PCI0.TBT1 })
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}
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#endif // SOC_INTEL_TIGERLAKE_S3
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#endif // D3COLD_SUPPORT
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}
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/*
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@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
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Method (_S0W, 0x0, NotSerialized)
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{
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#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
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#if CONFIG(D3COLD_SUPPORT)
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Return (0x4)
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#else
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Return (0x3)
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#endif // SOC_INTEL_TIGERLAKE_S3
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#endif // D3COLD_SUPPORT
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}
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/*
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@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
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*/
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Name (SD3C, 0)
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#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
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#if CONFIG(D3COLD_SUPPORT)
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Method (_PR0)
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{
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Return (Package () { \_SB.PCI0.D3C })
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@ -53,7 +53,7 @@ Method (_PR3)
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{
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Return (Package () { \_SB.PCI0.D3C })
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}
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#endif // SOC_INTEL_TIGERLAKE_S3
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#endif // D3COLD_SUPPORT
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/*
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* XHCI controller _DSM method
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