src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344
Cq-Depend: chrome-internal:1759167 Change-Id: Ib5784eb8c0f7c6e56950dad5c8254e00aa73cef4 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35245 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ronak Kanabar
Furquan Shaikh
parent
7e1f1a5130
commit
5f1786fc9c
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@ -1464,11 +1464,96 @@ typedef struct {
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**/
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UINT8 SerialIoUartDebugDataBits;
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/** Offset 0x0457 - ReservedPchPreMem
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/** Offset 0x0457 - Enable HD Audio DSP
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Enable/disable HD Audio DSP feature.
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$EN_DIS
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**/
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UINT8 PchHdaDspEnable;
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/** Offset 0x0458 - VC Type
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Virtual Channel Type Select: 0: VC0, 1: VC1.
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0: VC0, 1: VC1
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**/
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UINT8 PchHdaVcType;
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/** Offset 0x0459 - Universal Audio Architecture compliance for DSP enabled system
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0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
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driver or SST driver supported).
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$EN_DIS
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**/
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UINT8 PchHdaDspUaaCompliance;
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/** Offset 0x045A - Enable HD Audio Link
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Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
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$EN_DIS
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**/
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UINT8 PchHdaAudioLinkHda;
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/** Offset 0x045B - Enable HD Audio DMIC0 Link
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Deprecated.
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$EN_DIS
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**/
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UINT8 PchHdaAudioLinkDmic0;
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/** Offset 0x045C - Enable HD Audio DMIC1 Link
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Deprecated.
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$EN_DIS
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**/
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UINT8 PchHdaAudioLinkDmic1;
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/** Offset 0x045D - Enable HD Audio SSP0 Link
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Enable/disable HD Audio SSP0/I2S link. Muxed with HDA.
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$EN_DIS
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**/
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UINT8 PchHdaAudioLinkSsp0;
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/** Offset 0x045E - Enable HD Audio SSP1 Link
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Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2.
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$EN_DIS
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**/
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UINT8 PchHdaAudioLinkSsp1;
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/** Offset 0x045F - Enable HD Audio SSP2 Link
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Enable/disable HD Audio SSP2/I2S link.
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$EN_DIS
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**/
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UINT8 PchHdaAudioLinkSsp2;
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/** Offset 0x0460 - Enable HD Audio SoundWire#1 Link
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Enable/disable HD Audio SNDW1 link. Muxed with HDA.
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$EN_DIS
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**/
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UINT8 PchHdaAudioLinkSndw1;
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/** Offset 0x0461 - Enable HD Audio SoundWire#2 Link
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Enable/disable HD Audio SNDW2 link. Muxed with SSP1.
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$EN_DIS
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**/
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UINT8 PchHdaAudioLinkSndw2;
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/** Offset 0x0462 - Enable HD Audio SoundWire#3 Link
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Enable/disable HD Audio SNDW3 link. Muxed with DMIC1.
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$EN_DIS
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**/
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UINT8 PchHdaAudioLinkSndw3;
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/** Offset 0x0463 - Enable HD Audio SoundWire#4 Link
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Enable/disable HD Audio SNDW4 link. Muxed with DMIC0.
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$EN_DIS
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**/
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UINT8 PchHdaAudioLinkSndw4;
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/** Offset 0x0464 - Soundwire Clock Buffer GPIO RCOMP Setting
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0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.
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$EN_DIS
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**/
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UINT8 PchHdaSndwBufferRcomp;
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/** Offset 0x0465 - ReservedPchPreMem
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Reserved for Pch Pre-Mem
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$EN_DIS
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**/
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UINT8 ReservedPchPreMem[16];
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UINT8 ReservedPchPreMem[2];
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/** Offset 0x0467 - ISA Serial Base selection
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Select ISA Serial Base address. Default is 0x3F8.
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@ -2284,7 +2369,7 @@ typedef struct {
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Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
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Info & Verbose.
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0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
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Error Warnings and Info, 5:Load Error Warnings Info and Verbose
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Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
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**/
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UINT8 PcdSerialDebugLevel;
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@ -2390,13 +2475,27 @@ typedef struct {
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**/
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UINT8 Ddr4SkipRefreshEn;
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/** Offset 0x0510
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/** Offset 0x0510 - SerialDebugMrcLevel
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MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
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Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
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Info & Verbose.
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0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
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Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
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**/
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UINT8 SerialDebugMrcLevel;
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/** Offset 0x0511 - Enable HD Audio Sndw Link IO Control
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deprecated
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**/
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UINT8 PchHdaSndwLinkIoControlEnabled[4];
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/** Offset 0x0515
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**/
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UINT8 UnusedUpdSpace8[2];
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/** Offset 0x0512
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/** Offset 0x0517
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**/
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UINT8 ReservedFspmUpd[6];
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UINT8 ReservedFspmUpd[1];
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} FSP_M_CONFIG;
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/** Fsp M Test Configuration
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@ -1319,8 +1319,8 @@ typedef struct {
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UINT8 PmcModPhySusPgEnable;
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/** Offset 0x036F - SlpS0WithGbeSupport
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Enable/Disable SLP_S0 with GBE Support. Default is 0 when paired with WHL V0 stepping
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CPU and 1 for all other CPUs. 0: Disable, 1: Enable
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Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping
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CPU and 1 for PCH-H Series. 0: Disable, 1: Enable
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$EN_DIS
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**/
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UINT8 SlpS0WithGbeSupport;
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@ -2053,23 +2053,23 @@ typedef struct {
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UINT8 PchScsEmmcHs400TuningRequired;
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/** Offset 0x06A0 - Set HS400 Tuning Data Valid
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Set if HS400 Tuning Data Valid.
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Deprecated
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$EN_DIS
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**/
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UINT8 PchScsEmmcHs400DllDataValid;
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/** Offset 0x06A1 - Rx Strobe Delay Control
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Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
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Deprecated
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**/
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UINT8 PchScsEmmcHs400RxStrobeDll1;
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/** Offset 0x06A2 - Tx Data Delay Control
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Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
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Deprecated
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**/
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UINT8 PchScsEmmcHs400TxDataDll;
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/** Offset 0x06A3 - I/O Driver Strength
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Deprecated.
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Deprecated
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0:33 Ohm, 1:40 Ohm, 2:50 Ohm
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**/
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UINT8 PchScsEmmcHs400DriverStrength;
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@ -2440,11 +2440,30 @@ typedef struct {
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**/
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UINT8 ScsSdCardWpPinEnabled;
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/** Offset 0x074F - ReservedPchPostMem
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/** Offset 0x074F - Set SATA DEVSLP GPIO Reset Config
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Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset,
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0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte
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for each port, byte0 for port0, byte1 for port1, and so on.
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**/
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UINT8 SataPortsDevSlpResetConfig[8];
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/** Offset 0x0757 - Flash Configuration Lock Down
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Enable/disable flash lock down. If platform decides to skip this programming, it
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must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post.
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$EN_DIS
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**/
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UINT8 SpiFlashCfgLockDown;
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/** Offset 0x0758 - Enable HD Audio Sndw Link IO Control
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0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled
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**/
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UINT8 PchHdaSndwLinkIoControlEnabled[4];
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/** Offset 0x075C - ReservedPchPostMem
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Reserved for Pch Post-Mem
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$EN_DIS
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**/
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UINT8 ReservedPchPostMem[16];
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UINT8 ReservedPchPostMem[3];
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/** Offset 0x075F
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**/
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@ -3326,11 +3345,51 @@ typedef struct {
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**/
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UINT8 C3StateUnDemotion;
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/** Offset 0x08BF - ReservedCpuPostMemTest
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/** Offset 0x08BF - Ratio Limit Num Core 0
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Ratio Limit Num Core0: This register defines the active core ranges for each frequency point
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**/
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UINT8 RatioLimitNumCore0;
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/** Offset 0x08C0 - Ratio Limit Num Core 1
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Ratio Limit Num Core1: This register defines the active core ranges for each frequency point
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**/
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UINT8 RatioLimitNumCore1;
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/** Offset 0x08C1 - Ratio Limit Num Core 2
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Ratio Limit Num Core2: This register defines the active core ranges for each frequency point
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**/
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UINT8 RatioLimitNumCore2;
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/** Offset 0x08C2 - Ratio Limit Core 3
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Ratio Limit Num Core3: This register defines the active core ranges for each frequency point
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**/
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UINT8 RatioLimitNumCore3;
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/** Offset 0x08C3 - Ratio Limit Num Core 4
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Ratio Limit Num Core4: This register defines the active core ranges for each frequency point
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**/
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UINT8 RatioLimitNumCore4;
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/** Offset 0x08C4 - Ratio Limit Num Core 5
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Ratio Limit Num Core5: This register defines the active core ranges for each frequency point
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**/
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UINT8 RatioLimitNumCore5;
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/** Offset 0x08C5 - Ratio Limit Num Core 6
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Ratio Limit Num Core6: This register defines the active core ranges for each frequency point
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**/
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UINT8 RatioLimitNumCore6;
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/** Offset 0x08C6 - Ratio Limit Num Core 7
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Ratio Limit Num Core7: This register defines the active core ranges for each frequency point
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**/
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UINT8 RatioLimitNumCore7;
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/** Offset 0x08C7 - ReservedCpuPostMemTest
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Reserved for CPU Post-Mem Test
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$EN_DIS
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**/
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UINT8 ReservedCpuPostMemTest[19];
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UINT8 ReservedCpuPostMemTest[11];
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/** Offset 0x08D2 - SgxSinitDataFromTpm
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SgxSinitDataFromTpm default values
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@ -3338,8 +3397,7 @@ typedef struct {
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UINT8 SgxSinitDataFromTpm;
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/** Offset 0x08D3 - End of Post message
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Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
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EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI
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Deprecated
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0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
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**/
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UINT8 EndOfPostMessage;
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@ -3488,11 +3546,82 @@ typedef struct {
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**/
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UINT8 MctpBroadcastCycle;
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/** Offset 0x0A8A
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/** Offset 0x0A8A - Use DLL values from policy
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Set if FSP should use HS400 DLL values from policy
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$EN_DIS
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**/
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UINT8 UnusedUpdSpace29[2];
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UINT8 EmmcUseCustomDlls;
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/** Offset 0x0A8C
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/** Offset 0x0A8B
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**/
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UINT8 UnusedUpdSpace29;
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/** Offset 0x0A8C - Emmc Tx CMD Delay control register value
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Please see Tx CMD Delay Control register definition for help
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**/
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UINT32 EmmcTxCmdDelayRegValue;
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/** Offset 0x0A90 - Emmc Tx DATA Delay control 1 register value
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Please see Tx DATA Delay control 1 register definition for help
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**/
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UINT32 EmmcTxDataDelay1RegValue;
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/** Offset 0x0A94 - Emmc Tx DATA Delay control 2 register value
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Please see Tx DATA Delay control 2 register definition for help
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**/
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UINT32 EmmcTxDataDelay2RegValue;
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/** Offset 0x0A98 - Emmc Rx CMD + DATA Delay control 1 register value
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Please see Rx CMD + DATA Delay control 1 register definition for help
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**/
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UINT32 EmmcRxCmdDataDelay1RegValue;
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/** Offset 0x0A9C - Emmc Rx CMD + DATA Delay control 2 register value
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Please see Rx CMD + DATA Delay control 2 register definition for help
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**/
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UINT32 EmmcRxCmdDataDelay2RegValue;
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/** Offset 0x0AA0 - Emmc Rx Strobe Delay control register value
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Please see Rx Strobe Delay control register definition for help
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**/
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UINT32 EmmcRxStrobeDelayRegValue;
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/** Offset 0x0AA4 - Use tuned DLL values from policy
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Set if FSP should use HS400 DLL values from policy
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$EN_DIS
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**/
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UINT8 SdCardUseCustomDlls;
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/** Offset 0x0AA5
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**/
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UINT8 UnusedUpdSpace30[3];
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/** Offset 0x0AA8 - SdCard Tx CMD Delay control register value
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Please see Tx CMD Delay Control register definition for help
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**/
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UINT32 SdCardTxCmdDelayRegValue;
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/** Offset 0x0AAC - SdCard Tx DATA Delay control 1 register value
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Please see Tx DATA Delay control 1 register definition for help
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**/
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UINT32 SdCardTxDataDelay1RegValue;
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/** Offset 0x0AB0 - SdCard Tx DATA Delay control 2 register value
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Please see Tx DATA Delay control 2 register definition for help
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**/
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UINT32 SdCardTxDataDelay2RegValue;
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/** Offset 0x0AB4 - SdCard Rx CMD + DATA Delay control 1 register value
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Please see Rx CMD + DATA Delay control 1 register definition for help
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**/
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UINT32 SdCardRxCmdDataDelay1RegValue;
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/** Offset 0x0AB8 - SdCard Rx CMD + DATA Delay control 2 register value
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Please see Rx CMD + DATA Delay control 2 register definition for help
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**/
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UINT32 SdCardRxCmdDataDelay2RegValue;
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/** Offset 0x0ABC
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**/
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UINT8 ReservedFspsTestUpd[12];
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} FSP_S_TEST_CONFIG;
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@ -3513,11 +3642,11 @@ typedef struct {
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**/
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FSP_S_TEST_CONFIG FspsTestConfig;
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/** Offset 0x0A98
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/** Offset 0x0AC8
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**/
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UINT8 UnusedUpdSpace30[6];
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UINT8 UnusedUpdSpace31[6];
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/** Offset 0x0A9E
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/** Offset 0x0ACE
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**/
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UINT16 UpdTerminator;
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} FSPS_UPD;
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