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facebook/watson: Initial commit 

This adds another camelbackmountain_fsp derivative, along with a .fmd
file for the board. For now it's been tested to build and boot.

Change-Id: I9e8804264967c19f6b51fc44575b0db36f600f88
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
David Hendricks 2018-04-24 14:37:38 -07:00 committed by Philipp Deppenwiese
parent c1072f2fc7
commit 5f187dbe63
18 changed files with 557 additions and 0 deletions
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16
src/mainboard/facebook/Kconfig Normal file
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if VENDOR_FACEBOOK
choice
prompt "Mainboard model"
source "src/mainboard/facebook/*/Kconfig.name"
endchoice
source "src/mainboard/facebook/*/Kconfig"
config MAINBOARD_VENDOR
string
default "Facebook"
endif # VENDOR_FACEBOOK

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src/mainboard/facebook/Kconfig.name Normal file
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config VENDOR_FACEBOOK
bool "Facebook"

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src/mainboard/facebook/watson/Kconfig Normal file
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if BOARD_FACEBOOK_WATSON
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_INTEL_FSP_BROADWELL_DE
select BOARD_ROMSIZE_KB_16384
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select INTEGRATED_UART
select SERIRQ_CONTINUOUS_MODE
config MAINBOARD_DIR
string
default "facebook/watson"
config MAINBOARD_PART_NUMBER
string
default "Watson"
config IRQ_SLOT_COUNT
int
default 18
config CBFS_SIZE
hex
default 0x00800000
config VIRTUAL_ROM_SIZE
hex
# Set to CONFIG_ROM_SIZE*2 if using concatenated flash chips.
# See FSP's Kconfig for details.
default ROM_SIZE
config DRIVERS_UART_8250IO
def_bool n
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
endif # BOARD_FACEBOOK_WATSON

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src/mainboard/facebook/watson/Kconfig.name Normal file
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config BOARD_FACEBOOK_WATSON
bool "Watson"

16
src/mainboard/facebook/watson/Makefile.inc Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
ramstage-y += irqroute.c

20
src/mainboard/facebook/watson/acpi/mainboard.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
}

56
src/mainboard/facebook/watson/acpi/platform.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* The APM port can be used for generating software SMIs */
OperationRegion (APMP, SystemIO, 0xb2, 2)
Field (APMP, ByteAcc, NoLock, Preserve)
{
APMC, 8, // APM command
APMS, 8 // APM status
}
/* Port 80 POST */
OperationRegion (POST, SystemIO, 0x80, 1)
Field (POST, ByteAcc, Lock, Preserve)
{
DBG0, 8
}
Name(\APC1, Zero) // IIO IOAPIC
Name(\PICM, Zero) // IOAPIC/8259
Method(_PIC, 1)
{
Store(Arg0, PICM)
}
/* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
Method(_PTS,1)
{
}
/* The _WAK method is called on system wakeup */
Method(_WAK,1)
{
Return(Package(){0,0})
}

42
src/mainboard/facebook/watson/acpi_tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/ioapic.h>
#include <soc/acpi.h>
#include <soc/iomap.h>
unsigned long acpi_fill_madt(unsigned long current)
{
u32 i;
current = acpi_create_madt_lapics(current);
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8,
IOXAPIC1_BASE_ADDRESS, 0);
set_ioapic_id((u8 *)IOXAPIC1_BASE_ADDRESS, 8);
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9,
IOXAPIC2_BASE_ADDRESS, 24);
set_ioapic_id((u8 *)IOXAPIC2_BASE_ADDRESS, 9);
current = acpi_madt_irq_overrides(current);
for (i = 0; i < 16; i++)
current += acpi_create_madt_lapic_nmi(
(acpi_madt_lapic_nmi_t *)current, i, 0xD, 1);
return current;
}

25
src/mainboard/facebook/watson/board.fmd Normal file
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FLASH@0xff000000 0x1000000 {
SI_DESC@0x0 0x1000
IDPROM@0x1000 0x500
UNUSED_1@0x1500 0x1FB00
SI_ME@0x21000 0x3de000
UNUSED_2@0x400000 0x200000
SI_BIOS@0x600000 0xA00000 {
FMAP@0x0 0x1000
RW_MISC@0x1000 0xe000 {
RW_ELOG@0x0 0x4000
RW_VPD@0x4000 0x2000
RW_MISC_UNUSED@0x6000 0x5000
RW_NVRAM@0xc000 0x2000
}
UNIFIED_MRC_CACHE@0x10000 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
# This only exists to satisfy tools that specifically
# look for RO_VPD.
RO_VPD@0x30000 0x1000
UNUSED_3@0x31000 0x1CF000
COREBOOT(CBFS)@0x200000 0x800000
}
}

4
src/mainboard/facebook/watson/board_info.txt Normal file
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Board name: Watson
Category: server
ROM protocol: SPI
ROM socketed: yes

105
src/mainboard/facebook/watson/cmos.layout Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
# -----------------------------------------------------------------
entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
# -----------------------------------------------------------------
# Status Register A
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
# -----------------------------------------------------------------
# Status Register B
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
120 264 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused?
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 6 debug_level
#399 1 r 0 unused
# coreboot config options: check sums
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# -----------------------------------------------------------------
checksums
checksum 392 415 984

15
src/mainboard/facebook/watson/devicetree.cb Normal file
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chip soc/intel/fsp_broadwell_de
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 14.0 on end # xHCI Controller
device pci 19.0 on end # Gigabit LAN Controller
device pci 1d.0 on end # EHCI Controller
device pci 1f.0 on end # LPC Bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus Controller
device pci 1f.5 on end # SATA Controller
end
end

44
src/mainboard/facebook/watson/dsdt.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20110725 // OEM revision
)
{
#include "acpi/platform.asl"
Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 })
Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
Scope (\_SB)
{
Device (PCI0)
{
#include <acpi/southcluster.asl>
#include <acpi/pcie1.asl>
}
#include <acpi/uncore.asl>
}
#include "acpi/mainboard.asl"
}

28
src/mainboard/facebook/watson/fadt.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/acpi.h>
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
acpi_fill_in_fadt(fadt, facs, dsdt);
/* Platform specific customizations go here */
header->checksum = 0;
header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
}

18
src/mainboard/facebook/watson/irqroute.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "irqroute.h"
DEFINE_IRQ_ROUTES;

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src/mainboard/facebook/watson/irqroute.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef IRQROUTE_H
#define IRQROUTE_H
#include <soc/irq.h>
#include <soc/pci_devs.h>
#define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D)
/*
* Route each PIRQ[A-H] to a PIC IRQ[0-15]
* Reserved: 0, 1, 2, 8, 13
* ACPI/SCI: 9
*/
#define PIRQ_PIC_ROUTES \
PIRQ_PIC(A, 5), \
PIRQ_PIC(B, 6), \
PIRQ_PIC(C, 7), \
PIRQ_PIC(D, 10), \
PIRQ_PIC(E, 11), \
PIRQ_PIC(F, 12), \
PIRQ_PIC(G, 14), \
PIRQ_PIC(H, 15)
#endif /* IRQROUTE_H */

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src/mainboard/facebook/watson/mainboard.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
/*
* mainboard_enable is executed as first thing after enumerate_buses().
* This is the earliest point to add customization.
*/
static void mainboard_enable(struct device *dev)
{
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

45
src/mainboard/facebook/watson/romstage.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stddef.h>
#include <soc/romstage.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
/**
* /brief mainboard call for setup that needs to be done before fsp init
*
*/
void early_mainboard_romstage_entry(void)
{
}
/**
* /brief mainboard call for setup that needs to be done after fsp init
*
*/
void late_mainboard_romstage_entry(void)
{
}
/**
* /brief customize fsp parameters here if needed
*/
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
{
}