util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types
Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware table entries, so add those as a preparation for Sabrina support. Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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@ -260,6 +260,9 @@ amd_fw_entry amd_psp_fw_table[] = {
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{ .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB },
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{ .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB },
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{ .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB },
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{ .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB },
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{ .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB },
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{ .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB },
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{ .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB },
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{ .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB },
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{ .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB },
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@ -54,6 +54,9 @@ typedef enum _amd_fw_type {
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AMD_FW_SPL = 0x55,
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AMD_FW_DMCU_ERAM = 0x58,
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AMD_FW_DMCU_ISR = 0x59,
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AMD_FW_MSMU = 0x5a,
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AMD_FW_SPIROM_CFG = 0x5c,
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AMD_FW_DMCUB = 0x71,
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AMD_FW_PSP_BOOTLOADER_AB = 0x73,
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AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */
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AMD_FW_GEC,
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@ -306,6 +306,15 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
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} else if (strcmp(fw_name, "DMCUINTVECTORSDCN21_FILE") == 0) {
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fw_type = AMD_FW_DMCU_ISR;
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subprog = 0;
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} else if (strcmp(fw_name, "MSMU_FILE") == 0) {
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fw_type = AMD_FW_MSMU;
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subprog = 0;
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} else if (strcmp(fw_name, "DMCUB_FILE") == 0) {
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fw_type = AMD_FW_DMCUB;
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subprog = 0;
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} else if (strcmp(fw_name, "SPIROM_CONFIG_FILE") == 0) {
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fw_type = AMD_FW_SPIROM_CFG;
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subprog = 0;
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} else if (strcmp(fw_name, "PSP_KVM_ENGINE_DUMMY_FILE") == 0) {
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fw_type = AMD_FW_KVM_IMAGE;
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subprog = 0;
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