mainboard/intel: add leafhill board directory
This commit adds the initial scaffolding for the Intel Leafhill CRB with Apollo Lake silicon. The google/reef directory is used as a template. This commit only makes the minimum changes to Kconfig and Kconfig.name needed for the build bot to not have issues. Change-Id: I088edee0e94ecfb4666fa31e08dbcfd24a81891b Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18038 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Brenton Dong
Martin Roth
parent
b46c4ecaba
commit
5f1f0538cf
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@ -0,0 +1,108 @@
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config BOARD_GOOGLE_BASEBOARD_REEF
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def_bool n
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select SOC_INTEL_APOLLOLAKE
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select BOARD_ROMSIZE_KB_16384
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select I2C_TPM
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_HAS_I2C_TPM_CR50
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select TPM2
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select GOOGLE_SMBIOS_MAINBOARD_VERSION
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if BOARD_INTEL_LEAFHILL
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config BASEBOARD_REEF_LAPTOP
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def_bool n
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select SYSTEM_TYPE_LAPTOP
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x2
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config DRIVER_TPM_I2C_ADDR
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hex
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default 0x50
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config DRIVER_TPM_I2C_IRQ
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int
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default 60 # GPE0_DW1_28
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config CHROMEOS
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select HAS_RECOVERY_MRC_CACHE
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select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
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select LID_SWITCH if BASEBOARD_REEF_LAPTOP
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config DRIVERS_I2C_DA7219
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default y
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config DRIVERS_I2C_GENERIC
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default y
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config DRIVERS_I2C_WACOM
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default y
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config DRIVERS_PS2_KEYBOARD
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default y
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config DRIVERS_GENERIC_GPIO_REGULATOR
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default y
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config MAINBOARD_DIR
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string
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default intel/leafhill
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config VARIANT_DIR
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string
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default "reef"
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default "pyro" if BOARD_GOOGLE_PYRO
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default "snappy" if BOARD_GOOGLE_SNAPPY
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config DEVICETREE
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string
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default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO
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default "variants/snappy/devicetree.cb" if BOARD_GOOGLE_SNAPPY
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default "variants/baseboard/devicetree.cb"
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config MAINBOARD_PART_NUMBER
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string
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default "Reef"
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default "Pyro" if BOARD_GOOGLE_PYRO
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default "Snappy" if BOARD_GOOGLE_SNAPPY
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config MAINBOARD_FAMILY
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string
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default "Google_Reef"
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config GBB_HWID
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string
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depends on CHROMEOS
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default "REEF TEST 3240" if BOARD_GOOGLE_REEF
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default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO
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default "SNAPPY TEST 1088" if BOARD_GOOGLE_SNAPPY
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config MAX_CPUS
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int
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default 8
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config UART_FOR_CONSOLE
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int
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default 2
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config INCLUDE_NHLT_BLOBS
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bool "Include blobs for audio."
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select NHLT_DMIC_1CH_16B
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select NHLT_DMIC_2CH_16B
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select NHLT_DMIC_4CH_16B
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select NHLT_DA7219
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select NHLT_MAX98357
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config DRIVERS_GENERIC_MAX98357A
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default y
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endif # BOARD_INTEL_LEAFHILL
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@ -0,0 +1,4 @@
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config BOARD_INTEL_LEAFHILL
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bool "Leafhill"
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select BOARD_GOOGLE_BASEBOARD_REEF
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select BASEBOARD_REEF_LAPTOP
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@ -0,0 +1,19 @@
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bootblock-y += bootblock.c
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bootblock-y += ec.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-y += boardid.c
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ramstage-y += boardid.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += ec.c
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ramstage-y += mainboard.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@ -0,0 +1,14 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Blank file required by build system assumptions of this file being present.
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*/
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@ -0,0 +1,6 @@
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Vendor name: Google
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Board name: Reef Apollolake Reference Board
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Category: laptop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,29 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/variants.h>
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#include <boardid.h>
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#include <stddef.h>
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uint8_t board_id(void)
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{
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MAYBE_STATIC int id = -1;
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if (id < 0)
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id = variant_board_id();
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return id;
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}
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@ -0,0 +1,32 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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#include <ec/ec.h>
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#include <soc/lpc.h>
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#include <soc/gpio.h>
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#include <variant/ec.h>
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void bootblock_mainboard_init(void)
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{
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const struct pad_config *pads;
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size_t num;
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lpc_configure_pads();
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pads = variant_early_gpio_table(&num);
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gpio_configure_pads(pads, num);
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mainboard_ec_init();
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/variants.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
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{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
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{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{GPIO_EC_IN_RW, ACTIVE_HIGH,
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gpio_get(GPIO_EC_IN_RW), "EC in RW"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_write_protect_state(void)
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{
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/* Read PCH_WP GPIO. */
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return gpio_get(GPIO_PCH_WP);
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}
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void mainboard_chromeos_acpi_generate(void)
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{
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const struct cros_gpio *gpios;
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size_t num;
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gpios = variant_cros_gpios(&num);
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chromeos_acpi_gpio_generate(gpios, num);
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}
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@ -0,0 +1,53 @@
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FLASH 16M {
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WP_RO@0x0 0x400000 {
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SI_DESC@0x0 0x1000
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IFWI@0x1000 0x1ff000
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RO_VPD@0x200000 0x4000
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RO_SECTION@0x204000 0x1fc000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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COREBOOT(CBFS)@0x1000 0x17b000
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GBB@0x17c000 0x40000
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RO_UNUSED@0x1bc000 0x40000
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}
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}
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MISC_RW@0x400000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x21000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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RW_VAR_MRC_CACHE@0x20000 0x1000
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}
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RW_ELOG@0x21000 0x3000
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RW_SHARED@0x24000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD@0x28000 0x2000
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RW_NVRAM@0x2a000 0x6000
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}
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RW_SECTION_A@0x430000 0x480000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x46ffc0
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RW_FWID_A@0x47ffc0 0x40
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}
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RW_SECTION_B@0x8b0000 0x480000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x46ffc0
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RW_FWID_B@0x47ffc0 0x40
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}
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RW_LEGACY(CBFS)@0xd30000 0x200000
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BIOS_UNUSABLE@0xf30000 0x4f000
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DEVICE_EXTENSION@0xf7f000 0x80000
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# Currently, it is required that the BIOS region be a multiple of 8KiB.
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# This is required so that the recovery mechanism can find SIGN_CSE
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# region aligned to 4K at the center of BIOS region. Since the
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# descriptor at the beginning uses 4K and BIOS starts at an offset of
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# 4K, a hole of 4K is created towards the end of the flash to compensate
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# for the size requirement of BIOS region.
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# FIT tool thus creates descriptor with following regions:
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# Descriptor --> 0 to 4K
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# BIOS --> 4K to 0xf7f000
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# Device ext --> 0xf7f000 to 0xfff000
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UNUSED_HOLE@0xfff000 0x1000
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
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#include <variant/ec.h>
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#include <variant/gpio.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x05, // DSDT revision: ACPI v5.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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/* global NVS and variables */
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#include <soc/intel/apollolake/acpi/globalnvs.asl>
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/* CPU */
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#include <soc/intel/apollolake/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/apollolake/acpi/northbridge.asl>
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#include <soc/intel/apollolake/acpi/southbridge.asl>
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#include <soc/intel/apollolake/acpi/pch_hda.asl>
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}
|
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}
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|
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/* Chrome OS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* Chipset specific sleep states */
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#include <soc/intel/apollolake/acpi/sleepstates.asl>
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|
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
|
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
|
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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|
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/* Dynamic Platform Thermal Framework */
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Scope (\_SB)
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||||
{
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/* Per board variant specific definitions. */
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#include <variant/acpi/dptf.asl>
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/* Include soc specific DPTF changes */
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#include <soc/intel/apollolake/acpi/dptf.asl>
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/* Include common dptf ASL files */
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#include <soc/intel/common/acpi/dptf/dptf.asl>
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}
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}
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@ -0,0 +1,71 @@
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/*
|
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
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#include <console/console.h>
|
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec.h>
|
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#include <rules.h>
|
||||
#include <soc/lpc.h>
|
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#include <variant/ec.h>
|
||||
|
||||
static void ramstage_ec_init(void)
|
||||
{
|
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printk(BIOS_ERR, "mainboard: EC init\n");
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|
||||
if (acpi_is_wakeup_s3()) {
|
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google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
|
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MAINBOARD_EC_S3_WAKE_EVENTS);
|
||||
|
||||
/* Disable SMI and wake events */
|
||||
google_chromeec_set_smi_mask(0);
|
||||
|
||||
/* Clear pending events */
|
||||
while (google_chromeec_get_event() != 0)
|
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;
|
||||
|
||||
/* Restore SCI event mask */
|
||||
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
|
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} else {
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google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
|
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MAINBOARD_EC_S5_WAKE_EVENTS);
|
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}
|
||||
|
||||
/* Clear wake event mask */
|
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google_chromeec_set_wake_mask(0);
|
||||
}
|
||||
|
||||
static void bootblock_ec_init(void)
|
||||
{
|
||||
uint16_t ec_ioport_base;
|
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size_t ec_ioport_size;
|
||||
|
||||
/*
|
||||
* Set up LPC decoding for the ChromeEC I/O port ranges:
|
||||
* - Ports 62/66, 60/64, and 200->208
|
||||
* - ChromeEC specific communication I/O ports.
|
||||
*/
|
||||
lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
|
||||
google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
|
||||
lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
|
||||
}
|
||||
|
||||
void mainboard_ec_init(void)
|
||||
{
|
||||
if (ENV_RAMSTAGE)
|
||||
ramstage_ec_init();
|
||||
else if (ENV_BOOTBLOCK)
|
||||
bootblock_ec_init();
|
||||
}
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <boardid.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <ec/ec.h>
|
||||
#include <gpio.h>
|
||||
#include <nhlt.h>
|
||||
#include <smbios.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/nhlt.h>
|
||||
#include <string.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
#include <variant/ec.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
static void mainboard_init(void *chip_info)
|
||||
{
|
||||
int boardid;
|
||||
const struct pad_config *pads;
|
||||
size_t num;
|
||||
|
||||
boardid = board_id();
|
||||
printk(BIOS_INFO, "Board ID: %d\n", boardid);
|
||||
|
||||
pads = variant_gpio_table(&num);
|
||||
gpio_configure_pads(pads, num);
|
||||
|
||||
mainboard_ec_init();
|
||||
}
|
||||
|
||||
/*
|
||||
* There are 2 pins on reef-like boards that can be used for SKU'ing
|
||||
* board differences. They each have optional stuffing for a pullup and
|
||||
* a pulldown. This way we can generate 9 different values with the
|
||||
* 2 pins.
|
||||
*/
|
||||
static int board_sku(void)
|
||||
{
|
||||
static int board_sku_num = -1;
|
||||
gpio_t board_sku_gpios[] = {
|
||||
[1] = GPIO_17, [0] = GPIO_16,
|
||||
};
|
||||
const size_t num = ARRAY_SIZE(board_sku_gpios);
|
||||
|
||||
if (board_sku_num < 0)
|
||||
board_sku_num = gpio_base3_value(board_sku_gpios, num);
|
||||
|
||||
return board_sku_num;
|
||||
}
|
||||
|
||||
const char *smbios_mainboard_sku(void)
|
||||
{
|
||||
static char sku_str[5]; /* sku[0-8] */
|
||||
|
||||
snprintf(sku_str, sizeof(sku_str), "sku%d", board_sku());
|
||||
|
||||
return sku_str;
|
||||
}
|
||||
|
||||
void __attribute__((weak)) variant_nhlt_oem_overrides(const char **oem_id,
|
||||
const char **oem_table_id,
|
||||
uint32_t *oem_revision)
|
||||
{
|
||||
*oem_id = "reef";
|
||||
*oem_table_id = CONFIG_VARIANT_DIR;
|
||||
*oem_revision = board_sku();
|
||||
}
|
||||
|
||||
static unsigned long mainboard_write_acpi_tables(
|
||||
device_t device, unsigned long current, acpi_rsdp_t *rsdp)
|
||||
{
|
||||
uintptr_t start_addr;
|
||||
uintptr_t end_addr;
|
||||
struct nhlt *nhlt;
|
||||
const char *oem_id = NULL;
|
||||
const char *oem_table_id = NULL;
|
||||
uint32_t oem_revision = 0;
|
||||
|
||||
start_addr = current;
|
||||
|
||||
nhlt = nhlt_init();
|
||||
|
||||
if (nhlt == NULL)
|
||||
return start_addr;
|
||||
|
||||
variant_nhlt_init(nhlt);
|
||||
variant_nhlt_oem_overrides(&oem_id, &oem_table_id, &oem_revision);
|
||||
|
||||
end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr,
|
||||
oem_id, oem_table_id, oem_revision);
|
||||
|
||||
if (end_addr != start_addr)
|
||||
acpi_add_table(rsdp, (void *)start_addr);
|
||||
|
||||
return end_addr;
|
||||
}
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
|
||||
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.init = mainboard_init,
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
meminit_lpddr4_by_sku(&memupd->FspmConfig,
|
||||
variant_lpddr4_config(), variant_memory_sku());
|
||||
}
|
||||
|
||||
void mainboard_save_dimm_info(void)
|
||||
{
|
||||
save_lpddr4_dimm_info(variant_lpddr4_config(), variant_memory_sku());
|
||||
}
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2016 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <ec/google/chromeec/smm.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/smm.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <variant/ec.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
void mainboard_smi_gpi_handler(const struct gpi_status *sts)
|
||||
{
|
||||
if (gpi_status_get(sts, EC_SMI_GPI))
|
||||
chromeec_smi_process_events();
|
||||
}
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
const struct pad_config *pads;
|
||||
size_t num;
|
||||
|
||||
pads = variant_sleep_gpio_table(&num);
|
||||
gpio_configure_pads(pads, num);
|
||||
|
||||
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
|
||||
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
|
||||
MAINBOARD_EC_S5_WAKE_EVENTS);
|
||||
}
|
||||
|
||||
int mainboard_smi_apmc(u8 apmc)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
|
||||
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
|
||||
MAINBOARD_EC_SMI_EVENTS);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
bootblock-y += gpio.c
|
||||
|
||||
romstage-y += boardid.c
|
||||
romstage-y += memory.c
|
||||
|
||||
ramstage-y += boardid.c
|
||||
ramstage-y += gpio.c
|
||||
ramstage-y += nhlt.c
|
||||
|
||||
smm-y += gpio.c
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
|
||||
uint8_t __attribute__((weak)) variant_board_id(void)
|
||||
{
|
||||
return google_chromeec_get_board_version();
|
||||
}
|
||||
|
|
@ -0,0 +1,235 @@
|
|||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
|
||||
# Disable unused clkreq of PCIe root ports
|
||||
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
|
||||
# GPIO for PERST_0
|
||||
# If the Board has PERST_0 signal, assign the GPIO
|
||||
# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
|
||||
register "prt0_gpio" = "GPIO_122"
|
||||
|
||||
# EMMC TX DATA Delay 1
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [14:8] steps of delay for HS400, each 125ps.
|
||||
# [6:0] steps of delay for SDR104/HS200, each 125ps.
|
||||
register "emmc_tx_data_cntl1" = "0x0C16"
|
||||
|
||||
# EMMC TX DATA Delay 2
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [30:24] steps of delay for SDR50, each 125ps.
|
||||
# [22:16] steps of delay for DDR50, each 125ps.
|
||||
# [14:8] steps of delay for SDR25/HS50, each 125ps.
|
||||
# [6:0] steps of delay for SDR12, each 125ps.
|
||||
register "emmc_tx_data_cntl2" = "0x28162828"
|
||||
|
||||
# EMMC RX CMD/DATA Delay 1
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [30:24] steps of delay for SDR50, each 125ps.
|
||||
# [22:16] steps of delay for DDR50, each 125ps.
|
||||
# [14:8] steps of delay for SDR25/HS50, each 125ps.
|
||||
# [6:0] steps of delay for SDR12, each 125ps.
|
||||
register "emmc_rx_cmd_data_cntl1" = "0x00181717"
|
||||
|
||||
# EMMC RX CMD/DATA Delay 2
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [17:16] stands for Rx Clock before Output Buffer
|
||||
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
|
||||
# [6:0] steps of delay for HS200, each 125ps.
|
||||
register "emmc_rx_cmd_data_cntl2" = "0x10008"
|
||||
|
||||
# Enable DPTF
|
||||
register "dptf_enable" = "1"
|
||||
|
||||
# PL1 override 12000 mW: the energy calculation is wrong with the
|
||||
# current VR solution. Experiments show that SoC TDP max (6W) can
|
||||
# be reached when RAPL PL1 is set to 12W.
|
||||
register "tdp_pl1_override_mw" = "12000"
|
||||
# Set RAPL PL2 to 15W.
|
||||
register "tdp_pl2_override_mw" = "15000"
|
||||
|
||||
# Enable Audio Clock and Power gating
|
||||
register "hdaudio_clk_gate_enable" = "1"
|
||||
register "hdaudio_pwr_gate_enable" = "1"
|
||||
register "hdaudio_bios_config_lockdown" = "1"
|
||||
|
||||
# Enable lpss s0ix
|
||||
register "lpss_s0ix_enable" = "1"
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route, i.e., if this route changes then the affected GPE
|
||||
# offset bits also need to be changed. This sets the PMC register
|
||||
# GPE_CFG fields.
|
||||
register "gpe0_dw1" = "PMC_GPE_N_31_0"
|
||||
register "gpe0_dw2" = "PMC_GPE_N_63_32"
|
||||
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
|
||||
|
||||
# Enable I2C0 for audio codec at 400kHz
|
||||
register "i2c[0]" = "{
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 104,
|
||||
.fall_time_ns = 52,
|
||||
}"
|
||||
|
||||
# Enable I2C2 bus early for TPM at 400kHz
|
||||
register "i2c[2]" = "{
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 57,
|
||||
.fall_time_ns = 28,
|
||||
}"
|
||||
|
||||
# touchscreen at 400kHz
|
||||
register "i2c[3]" = "{
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 76,
|
||||
.fall_time_ns = 164,
|
||||
}"
|
||||
|
||||
# trackpad at 400kHz
|
||||
register "i2c[4]" = "{
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 114,
|
||||
.fall_time_ns = 164,
|
||||
}"
|
||||
|
||||
# digitizer at 400kHz
|
||||
register "i2c[5]" = "{
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 152,
|
||||
.fall_time_ns = 30,
|
||||
}"
|
||||
|
||||
# Minimum SLP S3 assertion width 28ms.
|
||||
register "slp_s3_assertion_width_usecs" = "28000"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # - Host Bridge
|
||||
device pci 00.1 on end # - DPTF
|
||||
device pci 00.2 on end # - NPK
|
||||
device pci 02.0 on end # - Gen
|
||||
device pci 03.0 on end # - Iunit
|
||||
device pci 0d.0 on end # - P2SB
|
||||
device pci 0d.1 on end # - PMC
|
||||
device pci 0d.2 on end # - SPI
|
||||
device pci 0d.3 on end # - Shared SRAM
|
||||
device pci 0e.0 on # - Audio
|
||||
chip drivers/generic/max98357a
|
||||
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
|
||||
register "sdmode_delay" = "5"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device pci 11.0 off end # - ISH
|
||||
device pci 12.0 off end # - SATA
|
||||
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
|
||||
device pci 13.1 off end # - Root Port 3 - PCIe-A 1
|
||||
device pci 13.2 off end # - Root Port 4 - PCIe-A 2
|
||||
device pci 13.3 off end # - Root Port 5 - PCIe-A 3
|
||||
device pci 14.0 on
|
||||
chip drivers/intel/wifi
|
||||
register "wake" = "GPE0_DW3_00"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end # - Root Port 0 - PCIe-B 0 - Wifi
|
||||
device pci 14.1 off end # - Root Port 1 - PCIe-B 1
|
||||
device pci 15.0 on end # - XHCI
|
||||
device pci 15.1 off end # - XDCI
|
||||
device pci 16.0 on # - I2C 0
|
||||
chip drivers/i2c/da7219
|
||||
register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)"
|
||||
register "btn_cfg" = "50"
|
||||
register "mic_det_thr" = "500"
|
||||
register "jack_ins_deb" = "20"
|
||||
register "jack_det_rate" = ""32ms_64ms""
|
||||
register "jack_rem_deb" = "1"
|
||||
register "a_d_btn_thr" = "0xa"
|
||||
register "d_b_btn_thr" = "0x16"
|
||||
register "b_c_btn_thr" = "0x21"
|
||||
register "c_mic_btn_thr" = "0x3e"
|
||||
register "btn_avg" = "4"
|
||||
register "adc_1bit_rpt" = "1"
|
||||
register "micbias_lvl" = "2600"
|
||||
register "mic_amp_in_sel" = ""diff""
|
||||
device i2c 1a on end
|
||||
end
|
||||
end
|
||||
device pci 16.1 on end # - I2C 1
|
||||
device pci 16.2 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end # - I2C 2
|
||||
device pci 16.3 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0001""
|
||||
register "desc" = ""ELAN Touchscreen""
|
||||
register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)"
|
||||
register "probed" = "1"
|
||||
register "pwr_mgmt_type" = "GPIO_EXPORT"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
|
||||
|
||||
chip drivers/generic/gpio_regulator
|
||||
register "name" = ""vcc33""
|
||||
register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
|
||||
register "enabled_on_boot" = "1"
|
||||
device generic 0 on end
|
||||
end
|
||||
|
||||
device i2c 10 on end
|
||||
end
|
||||
end # - I2C 3
|
||||
device pci 17.0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)"
|
||||
register "wake" = "GPE0_DW1_15"
|
||||
register "probed" = "1"
|
||||
device i2c 15 on end
|
||||
end
|
||||
end # - I2C 4
|
||||
device pci 17.1 on
|
||||
chip drivers/i2c/wacom
|
||||
register "generic" = "{
|
||||
.hid = WCOM50C1_HID,
|
||||
.cid = PNP0C50_CID,
|
||||
.desc = WCOM_DT_DESC,
|
||||
.irq = IRQ_LEVEL_LOW(GPIO_13_IRQ),
|
||||
}"
|
||||
register "hid_desc_reg_offset" = "0x1"
|
||||
device i2c 0x9 on end
|
||||
end
|
||||
end # - I2C 5
|
||||
device pci 17.2 off end # - I2C 6
|
||||
device pci 17.3 off end # - I2C 7
|
||||
device pci 18.0 on end # - UART 0
|
||||
device pci 18.1 on end # - UART 1
|
||||
device pci 18.2 on end # - UART 2
|
||||
device pci 18.3 off end # - UART 3
|
||||
device pci 19.0 on end # - SPI 0
|
||||
device pci 19.1 off end # - SPI 1
|
||||
device pci 19.2 off end # - SPI 2
|
||||
device pci 1a.0 on end # - PWM
|
||||
device pci 1b.0 on end # - SDCARD
|
||||
device pci 1c.0 on end # - eMMC
|
||||
device pci 1e.0 off end # - SDIO
|
||||
device pci 1f.0 on # - LPC
|
||||
chip ec/google/chromeec
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # - SMBUS
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,391 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
|
||||
/*
|
||||
* Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
|
||||
* table found in EDS vol 1, but some pins aren't grouped functionally in
|
||||
* the table so those were moved for more logical grouping.
|
||||
*/
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* PCIE_WAKE[0:3]_N */
|
||||
PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE), /* WLAN */
|
||||
PAD_CFG_GPI(GPIO_206, UP_20K, DEEP), /* Unused */
|
||||
PAD_CFG_GPI(GPIO_207, UP_20K, DEEP), /* Unused */
|
||||
PAD_CFG_GPI(GPIO_208, UP_20K, DEEP), /* Unused */
|
||||
|
||||
/* EMMC interface */
|
||||
PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */
|
||||
PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */
|
||||
PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */
|
||||
PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */
|
||||
PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */
|
||||
PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */
|
||||
PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */
|
||||
PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */
|
||||
PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */
|
||||
PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */
|
||||
PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */
|
||||
|
||||
/* SDIO -- unused. */
|
||||
PAD_CFG_GPI(GPIO_166, UP_20K, DEEP), /* SDIO_CLK */
|
||||
PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */
|
||||
/* Configure SDIO to enable power gating */
|
||||
PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */
|
||||
PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */
|
||||
PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */
|
||||
PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */
|
||||
|
||||
/* SDCARD */
|
||||
/* Pull down clock by 20K */
|
||||
PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */
|
||||
PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */
|
||||
PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */
|
||||
PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */
|
||||
PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */
|
||||
/* Card detect is active LOW. Pull up by 20K */
|
||||
PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */
|
||||
PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */
|
||||
/* CLK feedback, internal signal, needs 20K pull down */
|
||||
PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */
|
||||
/* No h/w write proect for uSD cards, pull down by 20K */
|
||||
PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1), /* SDCARD_LVL_WP */
|
||||
/* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */
|
||||
PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */
|
||||
|
||||
/* SMBus -- unused. */
|
||||
PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */
|
||||
PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP), /* SMB_CLK */
|
||||
PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */
|
||||
|
||||
/* LPC */
|
||||
PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */
|
||||
PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */
|
||||
PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */
|
||||
PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */
|
||||
PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */
|
||||
PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */
|
||||
PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */
|
||||
PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */
|
||||
PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */
|
||||
|
||||
/* I2C0 - Audio */
|
||||
PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* LPSS_I2C0_SDA */
|
||||
PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* LPSS_I2C0_SCL */
|
||||
|
||||
/* I2C1 - NFC with external pulls */
|
||||
PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1), /* LPSS_I2C1_SDA */
|
||||
PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1), /* LPSS_I2C1_SCL */
|
||||
|
||||
/* I2C2 - TPM */
|
||||
PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
|
||||
PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
|
||||
|
||||
/* I2C3 - touch */
|
||||
PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1), /* LPSS_I2C3_SDA */
|
||||
PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1), /* LPSS_I2C3_SCL */
|
||||
|
||||
/* I2C4 - trackpad */
|
||||
PAD_CFG_NF(GPIO_132, UP_2K, DEEP, NF1), /* LPSS_I2C4_SDA */
|
||||
PAD_CFG_NF(GPIO_133, UP_2K, DEEP, NF1), /* LPSS_I2C4_SCL */
|
||||
|
||||
/* I2C5 -- pen with external pulls */
|
||||
PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1), /* LPSS_I2C5_SDA */
|
||||
PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1), /* LPSS_I2C5_SCL */
|
||||
|
||||
/* I2C6-7 -- unused. */
|
||||
PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */
|
||||
PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */
|
||||
PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */
|
||||
PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* LPSS_I2C7_SCL */
|
||||
|
||||
/* Audio Amp - I2S6 */
|
||||
PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2), /* ISH_GPIO_0 - I2S6_BCLK */
|
||||
PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2), /* ISH_GPIO_1 - I2S6_WS_SYNC */
|
||||
PAD_CFG_GPI(GPIO_148, UP_20K, DEEP), /* ISH_GPIO_2 - unused */
|
||||
PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2), /* ISH_GPIO_3 - I2S6_SDO */
|
||||
|
||||
/* NFC Reset */
|
||||
PAD_CFG_GPO(GPIO_150, 1, DEEP), /* ISH_GPIO_4 */
|
||||
|
||||
PAD_CFG_GPI(GPIO_151, UP_20K, DEEP), /* ISH_GPIO_5 - unused */
|
||||
|
||||
/* Touch enable */
|
||||
PAD_CFG_GPO(GPIO_152, 1, DEEP), /* ISH_GPIO_6 */
|
||||
|
||||
PAD_CFG_GPI(GPIO_153, UP_20K, DEEP), /* ISH_GPIO_7 - unused */
|
||||
PAD_CFG_GPI(GPIO_154, UP_20K, DEEP), /* ISH_GPIO_8 - unused */
|
||||
PAD_CFG_GPI(GPIO_155, UP_20K, DEEP), /* ISH_GPIO_9 - unused */
|
||||
|
||||
/* PCIE_CLKREQ[0:3]_N */
|
||||
PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1), /* WLAN with external pull */
|
||||
PAD_CFG_GPI(GPIO_210, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_GPI(GPIO_211, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_GPI(GPIO_212, UP_20K, DEEP), /* unused */
|
||||
|
||||
/* OSC_CLK_OUT_[0:4] -- unused */
|
||||
PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP),
|
||||
|
||||
/* PMU Signals */
|
||||
PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP), /* PMU_AC_PRESENT - unused */
|
||||
PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */
|
||||
PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */
|
||||
PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */
|
||||
PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */
|
||||
PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), /* PMU_SLP_S0_N */
|
||||
PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */
|
||||
PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */
|
||||
PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */
|
||||
PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */
|
||||
PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */
|
||||
PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */
|
||||
|
||||
/* DDI[0:1] SDA and SCL -- unused */
|
||||
PAD_CFG_GPI(GPIO_187, UP_20K, DEEP), /* HV_DDI0_DDC_SDA */
|
||||
PAD_CFG_GPI(GPIO_188, UP_20K, DEEP), /* HV_DDI0_DDC_SCL */
|
||||
PAD_CFG_GPI(GPIO_189, UP_20K, DEEP), /* HV_DDI1_DDC_SDA */
|
||||
PAD_CFG_GPI(GPIO_190, UP_20K, DEEP), /* HV_DDI1_DDC_SCL */
|
||||
|
||||
/* MIPI I2C -- unused */
|
||||
PAD_CFG_GPI(GPIO_191, UP_20K, DEEP), /* MIPI_I2C_SDA */
|
||||
PAD_CFG_GPI(GPIO_192, UP_20K, DEEP), /* MIPI_I2C_SCL */
|
||||
|
||||
/* Panel 0 control */
|
||||
PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PNL0_VDDEN */
|
||||
PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PNL0_BKLTEN */
|
||||
PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PNL0_BKLTCTL */
|
||||
|
||||
/* Panel 1 control -- unused */
|
||||
PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1), /* PNL1_VDDEN */
|
||||
PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1), /* PNL1_BKLTEN */
|
||||
PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1), /* PNL1_BKLTCTL */
|
||||
|
||||
/* Hot plug detect. */
|
||||
PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */
|
||||
PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */
|
||||
|
||||
/* MDSI signals -- unused */
|
||||
PAD_CFG_GPI(GPIO_201, UP_20K, DEEP), /* MDSI_A_TE */
|
||||
PAD_CFG_GPI(GPIO_202, UP_20K, DEEP), /* MDSI_A_TE */
|
||||
|
||||
/* USB overcurrent pins. */
|
||||
PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */
|
||||
PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */
|
||||
|
||||
/* PMC SPI -- almost entirely unused */
|
||||
PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP),
|
||||
PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* HV_DDI2_HPD -- EDP HPD */
|
||||
PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP),
|
||||
|
||||
/* PMIC Signals Unused signals related to an old PMIC interface */
|
||||
PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE), /* PMIC_RESET_B */
|
||||
PAD_CFG_GPI(GPIO_213, NONE, DEEP), /* unused external pull */
|
||||
PAD_CFG_GPI(GPIO_214, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_GPI(GPIO_215, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), /* THERMTRIP_N */
|
||||
PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */
|
||||
PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), /* PMIC_I2C_SCL */
|
||||
PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), /* PMIC_I2C_SDA */
|
||||
|
||||
/* I2S1 -- largely unused */
|
||||
PAD_CFG_GPI(GPIO_74, UP_20K, DEEP), /* I2S1_MCLK */
|
||||
PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */
|
||||
PAD_CFG_GPO(GPIO_76, 0, DEEP), /* I2S1_WS_SYNC -- SPK_PA_EN */
|
||||
PAD_CFG_GPI(GPIO_77, UP_20K, DEEP), /* I2S1_SDI */
|
||||
PAD_CFG_GPI(GPIO_78, UP_20K, DEEP), /* I2S1_SDO */
|
||||
|
||||
/* DMIC or I2S4 */
|
||||
PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_A1 */
|
||||
PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_B1 */
|
||||
PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_1 */
|
||||
PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* unused -- strap */
|
||||
PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_2 */
|
||||
|
||||
/* I2S2 -- Headset amp */
|
||||
PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1), /* AVS_I2S2_MCLK */
|
||||
PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1), /* AVS_I2S2_BCLK */
|
||||
PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1), /* AVS_I2S2_SW_SYNC */
|
||||
PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1), /* AVS_I2S2_SDI */
|
||||
PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1), /* AVS_I2S2_SDO */
|
||||
|
||||
/* I2S3 -- largely unused. */
|
||||
PAD_CFG_GPI(GPIO_89, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_GPI(GPIO_90, UP_20K, DEEP), /* GPS_HOST_WAKE */
|
||||
PAD_CFG_GPO(GPIO_91, 1, DEEP), /* GPS_EN */
|
||||
PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* unused -- strap */
|
||||
|
||||
/* Fast SPI */
|
||||
PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */
|
||||
PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */
|
||||
PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */
|
||||
PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */
|
||||
PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */
|
||||
PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */
|
||||
PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */
|
||||
|
||||
/* SIO_SPI_0 - Used for FP */
|
||||
PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */
|
||||
PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */
|
||||
PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
|
||||
PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */
|
||||
PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */
|
||||
|
||||
/* SIO_SPI_1 -- largely unused */
|
||||
PAD_CFG_GPI(GPIO_111, UP_20K, DEEP), /* SIO_SPI_1_CLK */
|
||||
PAD_CFG_GPI(GPIO_112, UP_20K, DEEP), /* SIO_SPI_1_FS0 */
|
||||
PAD_CFG_GPI(GPIO_113, UP_20K, DEEP), /* SIO_SPI_1_FS1 */
|
||||
/* Headset interrupt */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP), /* SIO_SPI_1_RXD */
|
||||
PAD_CFG_GPI(GPIO_117, UP_20K, DEEP), /* SIO_SPI_1_TXD */
|
||||
|
||||
/* SIO_SPI_2 -- unused */
|
||||
PAD_CFG_GPI(GPIO_118, UP_20K, DEEP), /* SIO_SPI_2_CLK */
|
||||
PAD_CFG_GPI(GPIO_119, UP_20K, DEEP), /* SIO_SPI_2_FS0 */
|
||||
PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* SIO_SPI_2_FS1 */
|
||||
PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* SIO_SPI_2_FS2 */
|
||||
/* WLAN_PE_RST - default to deasserted. */
|
||||
PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */
|
||||
PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* SIO_SPI_2_TXD */
|
||||
|
||||
/* Debug tracing. */
|
||||
PAD_CFG_GPI(GPIO_0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPIO_1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPIO_2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL), /* FP_INT */
|
||||
PAD_CFG_GPI(GPIO_4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPIO_5, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPIO_6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPIO_7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPIO_8, UP_20K, DEEP),
|
||||
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */
|
||||
PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* Board phase enforcement */
|
||||
PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */
|
||||
PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_13, UP_20K, DEEP), /* PEN_INT_ODL */
|
||||
PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */
|
||||
PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */
|
||||
PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* 1 vs 4 DMIC config */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */
|
||||
PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */
|
||||
PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, LEVEL), /* EC wake */
|
||||
PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_GPI(GPIO_24, UP_20K, DEEP), /* PEN_PDCT_ODL */
|
||||
PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */
|
||||
PAD_CFG_GPO(GPIO_29, 1, DEEP), /* FP reset */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP), /* KB IRQ */
|
||||
PAD_CFG_GPO(GPIO_31, 0, DEEP), /* NFC FW DL */
|
||||
PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5), /* SUS_CLK2 */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */
|
||||
PAD_CFG_GPI(GPIO_34, UP_20K, DEEP), /* unused */
|
||||
PAD_CFG_GPO(GPIO_35, 0, DEEP), /* PEN_RESET - active high */
|
||||
PAD_CFG_GPO(GPIO_36, 0, DEEP), /* touch reset */
|
||||
PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */
|
||||
|
||||
/* LPSS_UART[0:2] */
|
||||
PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/
|
||||
/* Next 2 are straps. */
|
||||
PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */
|
||||
PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */
|
||||
PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */
|
||||
PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */
|
||||
PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */
|
||||
PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */
|
||||
PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */
|
||||
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */
|
||||
PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */
|
||||
PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */
|
||||
PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */
|
||||
|
||||
/* Camera interface -- completely unused. */
|
||||
PAD_CFG_GPI(GPIO_62, UP_20K, DEEP), /* GP_CAMERASB00 */
|
||||
PAD_CFG_GPI(GPIO_63, UP_20K, DEEP), /* GP_CAMERASB01 */
|
||||
PAD_CFG_GPI(GPIO_64, UP_20K, DEEP), /* GP_CAMERASB02 */
|
||||
PAD_CFG_GPI(GPIO_65, UP_20K, DEEP), /* GP_CAMERASB03 */
|
||||
PAD_CFG_GPI(GPIO_66, UP_20K, DEEP), /* GP_CAMERASB04 */
|
||||
PAD_CFG_GPI(GPIO_67, UP_20K, DEEP), /* GP_CAMERASB05 */
|
||||
PAD_CFG_GPI(GPIO_68, UP_20K, DEEP), /* GP_CAMERASB06 */
|
||||
PAD_CFG_GPI(GPIO_69, UP_20K, DEEP), /* GP_CAMERASB07 */
|
||||
PAD_CFG_GPI(GPIO_70, UP_20K, DEEP), /* GP_CAMERASB08 */
|
||||
PAD_CFG_GPI(GPIO_71, UP_20K, DEEP), /* GP_CAMERASB09 */
|
||||
PAD_CFG_GPI(GPIO_72, UP_20K, DEEP), /* GP_CAMERASB10 */
|
||||
PAD_CFG_GPI(GPIO_73, UP_20K, DEEP), /* GP_CAMERASB11 */
|
||||
};
|
||||
|
||||
const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
/* GPIOs needed prior to ramstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */
|
||||
/* I2C2 - TPM */
|
||||
PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
|
||||
PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */
|
||||
/* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */
|
||||
PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */
|
||||
};
|
||||
|
||||
const struct pad_config * __attribute__((weak))
|
||||
variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
/* GPIO settings before entering sleep. */
|
||||
static const struct pad_config sleep_gpio_table[] = {
|
||||
PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */
|
||||
};
|
||||
|
||||
const struct pad_config * __attribute__((weak))
|
||||
variant_sleep_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(sleep_gpio_table);
|
||||
return sleep_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
|
||||
CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME),
|
||||
CROS_GPIO_PE_AH(PAD_N(GPIO_SHIP_MODE), GPIO_COMM_N_NAME),
|
||||
};
|
||||
|
||||
const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(cros_gpios);
|
||||
return cros_gpios;
|
||||
}
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define DPTF_CPU_PASSIVE 95
|
||||
#define DPTF_CPU_CRITICAL 103
|
||||
#define DPTF_CPU_ACTIVE_AC0 90
|
||||
#define DPTF_CPU_ACTIVE_AC1 80
|
||||
#define DPTF_CPU_ACTIVE_AC2 70
|
||||
#define DPTF_CPU_ACTIVE_AC3 60
|
||||
#define DPTF_CPU_ACTIVE_AC4 50
|
||||
|
||||
#define DPTF_TSR0_SENSOR_ID 0
|
||||
#define DPTF_TSR0_SENSOR_NAME "Battery"
|
||||
#define DPTF_TSR0_PASSIVE 120
|
||||
#define DPTF_TSR0_CRITICAL 125
|
||||
|
||||
#define DPTF_TSR1_SENSOR_ID 1
|
||||
#define DPTF_TSR1_SENSOR_NAME "Ambient"
|
||||
#define DPTF_TSR1_PASSIVE 45
|
||||
#define DPTF_TSR1_CRITICAL 75
|
||||
|
||||
#define DPTF_TSR2_SENSOR_ID 2
|
||||
#define DPTF_TSR2_SENSOR_NAME "Charger"
|
||||
#define DPTF_TSR2_PASSIVE 55
|
||||
#define DPTF_TSR2_CRITICAL 90
|
||||
|
||||
#define DPTF_ENABLE_CHARGER
|
||||
|
||||
/* Charger performance states, board-specific values from charger and EC */
|
||||
Name (CHPS, Package () {
|
||||
Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
|
||||
Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
|
||||
Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
|
||||
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
|
||||
Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
|
||||
})
|
||||
|
||||
Name (DTRT, Package () {
|
||||
/* CPU Throttle Effect on CPU */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 30, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 0 */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
|
||||
|
||||
#ifdef DPTF_ENABLE_CHARGER
|
||||
/* Charger Effect on Temp Sensor 2 */
|
||||
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 },
|
||||
#endif
|
||||
|
||||
/* CPU Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 80, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 2 */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 },
|
||||
})
|
||||
|
||||
Name (MPPC, Package ()
|
||||
{
|
||||
0x2, /* Revision */
|
||||
Package () { /* Power Limit 1 */
|
||||
0, /* PowerLimitIndex, 0 for Power Limit 1 */
|
||||
3000, /* PowerLimitMinimum */
|
||||
12000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
200 /* StepSize */
|
||||
},
|
||||
Package () { /* Power Limit 2 */
|
||||
1, /* PowerLimitIndex, 1 for Power Limit 2 */
|
||||
8000, /* PowerLimitMinimum */
|
||||
8000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
1000 /* StepSize */
|
||||
}
|
||||
})
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef BASEBOARD_EC_H
|
||||
#define BASEBOARD_EC_H
|
||||
|
||||
#include <variant/gpio.h>
|
||||
#include <ec/google/chromeec/ec_commands.h>
|
||||
|
||||
#define MAINBOARD_EC_SCI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU))
|
||||
|
||||
#define MAINBOARD_EC_SMI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
|
||||
|
||||
/* EC can wake from S5 with lid or power button */
|
||||
#define MAINBOARD_EC_S5_WAKE_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
|
||||
|
||||
/* EC can wake from S3 with lid or power button or key press */
|
||||
#define MAINBOARD_EC_S3_WAKE_EVENTS \
|
||||
(MAINBOARD_EC_S5_WAKE_EVENTS |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
|
||||
|
||||
/* Log EC wake events plus EC shutdown events */
|
||||
#define MAINBOARD_EC_LOG_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
|
||||
|
||||
/*
|
||||
* ACPI related definitions for ASL code.
|
||||
*/
|
||||
|
||||
/* Enable EC backed ALS device in ACPI */
|
||||
#define EC_ENABLE_ALS_DEVICE
|
||||
|
||||
/* Enable EC backed PD MCU device in ACPI */
|
||||
#define EC_ENABLE_PD_MCU_DEVICE
|
||||
|
||||
/* Enable LID switch and provide wake pin for EC */
|
||||
#define EC_ENABLE_LID_SWITCH
|
||||
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
|
||||
|
||||
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
|
||||
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
|
||||
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef BASEBOARD_GPIO_H
|
||||
#define BASEBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/*
|
||||
* GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
|
||||
* which is North community
|
||||
*/
|
||||
#define EC_SCI_GPI GPE0_DW1_11
|
||||
|
||||
/* EC SMI */
|
||||
#define EC_SMI_GPI GPIO_49
|
||||
|
||||
/*
|
||||
* On lidopen/lidclose GPIO_22 from North Community gets toggled and
|
||||
* is used in _PRW to wake up device from sleep. GPIO_22 maps to
|
||||
* group GPIO_GPE_N_31_0 and the pad is configured as SCI with
|
||||
* EDGE_SINGLE and INVERT.
|
||||
*/
|
||||
#define GPE_EC_WAKE GPE0_DW1_22
|
||||
|
||||
/* Write Protect and indication if EC is in RW code. */
|
||||
#define GPIO_PCH_WP GPIO_75
|
||||
#define GPIO_EC_IN_RW GPIO_41
|
||||
/* Determine if board is in final shipping mode. */
|
||||
#define GPIO_SHIP_MODE GPIO_10
|
||||
|
||||
/* Memory SKU GPIOs. */
|
||||
#define MEM_CONFIG3 GPIO_45
|
||||
#define MEM_CONFIG2 GPIO_38
|
||||
#define MEM_CONFIG1 GPIO_102
|
||||
#define MEM_CONFIG0 GPIO_101
|
||||
|
||||
/* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */
|
||||
#define DMIC_CONFIG_PIN GPIO_17
|
||||
|
||||
#endif /* BASEBOARD_GPIO_H */
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef BASEBOARD_VARIANTS_H
|
||||
#define BASEBOARD_VARIANTS_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <stdint.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
/* Return the board id for the current variant board. */
|
||||
uint8_t variant_board_id(void);
|
||||
|
||||
/* The next set of functions return the gpio table and fill in the number of
|
||||
* entries for each table. */
|
||||
const struct pad_config *variant_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_sleep_gpio_table(size_t *num);
|
||||
|
||||
/* Baseboard default swizzle. Can be reused if swizzle is same. */
|
||||
extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle;
|
||||
/* Return LPDDR4 configuration structure. */
|
||||
const struct lpddr4_cfg *variant_lpddr4_config(void);
|
||||
/* Return memory SKU for the board. */
|
||||
size_t variant_memory_sku(void);
|
||||
|
||||
/* Return ChromeOS gpio table and fill in number of entries. */
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num);
|
||||
|
||||
/* Seed the NHLT tables with the board specific information. */
|
||||
struct nhlt;
|
||||
void variant_nhlt_oem_overrides(const char **oem_id,
|
||||
const char **oem_table_id, uint32_t *oem_revision);
|
||||
void variant_nhlt_init(struct nhlt *nhlt);
|
||||
|
||||
#endif /* BASEBOARD_VARIANTS_H */
|
||||
|
|
@ -0,0 +1,155 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
|
||||
/* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
|
||||
.phys[LP4_PHYS_CH0A] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH0B] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH1A] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH1B] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 },
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* The strings in the part_num field aren't necessarily the exact part
|
||||
* numbers used in all the designs. The reason is that the mosys userland
|
||||
* tool uses these strings for dumping more information. Different speed bins
|
||||
* could change in future systems, but the strings still need to match.
|
||||
*/
|
||||
static const struct lpddr4_sku skus[] = {
|
||||
/*
|
||||
* K4F6E304HB-MG - both logical channels While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate
|
||||
* the deneisty as 8Gb per rank.
|
||||
*/
|
||||
[0] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "K4F6E304HB-MGCJ",
|
||||
},
|
||||
/* K4F8E304HB-MG - both logical channels */
|
||||
[1] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "K4F8E304HB-MGCJ",
|
||||
},
|
||||
/*
|
||||
* MT53B512M32D2NP - both logical channels. While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate
|
||||
* the deneisty as 8Gb per rank.
|
||||
*/
|
||||
[2] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "MT53B512M32D2NP",
|
||||
},
|
||||
/* MT53B256M32D1NP - both logical channels */
|
||||
[3] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "MT53B256M32D1NP",
|
||||
},
|
||||
/*
|
||||
* H9HCNNNBPUMLHR - both logical channels. While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate the
|
||||
* density as 8Gb per rank.
|
||||
*/
|
||||
[4] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "H9HCNNNBPUMLHR",
|
||||
},
|
||||
/* H9HCNNN8KUMLHR - both logical channels */
|
||||
[5] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "H9HCNNN8KUMLHR",
|
||||
},
|
||||
};
|
||||
|
||||
static const struct lpddr4_cfg lp4cfg = {
|
||||
.skus = skus,
|
||||
.num_skus = ARRAY_SIZE(skus),
|
||||
.swizzle_config = &baseboard_lpddr4_swizzle,
|
||||
};
|
||||
|
||||
const struct lpddr4_cfg * __attribute__((weak)) variant_lpddr4_config(void)
|
||||
{
|
||||
return &lp4cfg;
|
||||
}
|
||||
|
||||
size_t __attribute__((weak)) variant_memory_sku(void)
|
||||
{
|
||||
gpio_t pads[] = {
|
||||
[3] = MEM_CONFIG3, [2] = MEM_CONFIG2,
|
||||
[1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
|
||||
};
|
||||
|
||||
/* Need internal pullups enabled as only pulldown stuffing options
|
||||
* exist. */
|
||||
return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
|
||||
}
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <console/console.h>
|
||||
#include <nhlt.h>
|
||||
#include <soc/nhlt.h>
|
||||
#include <gpio.h>
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
|
||||
{
|
||||
/* 1-dmic configuration */
|
||||
if (!nhlt_soc_add_dmic_array(nhlt, 1))
|
||||
printk(BIOS_ERR, "Added 1CH DMIC array.\n");
|
||||
/* 2-dmic configuration */
|
||||
if (!nhlt_soc_add_dmic_array(nhlt, 2))
|
||||
printk(BIOS_ERR, "Added 2CH DMIC array.\n");
|
||||
/* 4-dmic configuration */
|
||||
if (!nhlt_soc_add_dmic_array(nhlt, 4))
|
||||
printk(BIOS_ERR, "Added 4CH DMIC array.\n");
|
||||
/* Dialog for Headset codec.
|
||||
* Headset codec is bi-directional but uses the same configuration
|
||||
* settings for render and capture endpoints.
|
||||
*/
|
||||
if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
|
||||
printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
|
||||
|
||||
/* MAXIM Smart Amps for left and right speakers. */
|
||||
if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5))
|
||||
printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
|
||||
}
|
||||
|
|
@ -0,0 +1 @@
|
|||
romstage-y += memory.c
|
||||
|
|
@ -0,0 +1,211 @@
|
|||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
|
||||
# Disable unused clkreq of PCIe root ports
|
||||
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
|
||||
# GPIO for PERST_0
|
||||
# If the Board has PERST_0 signal, assign the GPIO
|
||||
# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
|
||||
register "prt0_gpio" = "GPIO_122"
|
||||
|
||||
# EMMC TX DATA Delay 1
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [14:8] steps of delay for HS400, each 125ps.
|
||||
# [6:0] steps of delay for SDR104/HS200, each 125ps.
|
||||
register "emmc_tx_data_cntl1" = "0x0C16"
|
||||
|
||||
# EMMC TX DATA Delay 2
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [30:24] steps of delay for SDR50, each 125ps.
|
||||
# [22:16] steps of delay for DDR50, each 125ps.
|
||||
# [14:8] steps of delay for SDR25/HS50, each 125ps.
|
||||
# [6:0] steps of delay for SDR12, each 125ps.
|
||||
register "emmc_tx_data_cntl2" = "0x28162828"
|
||||
|
||||
# EMMC RX CMD/DATA Delay 1
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [30:24] steps of delay for SDR50, each 125ps.
|
||||
# [22:16] steps of delay for DDR50, each 125ps.
|
||||
# [14:8] steps of delay for SDR25/HS50, each 125ps.
|
||||
# [6:0] steps of delay for SDR12, each 125ps.
|
||||
register "emmc_rx_cmd_data_cntl1" = "0x00181717"
|
||||
|
||||
# EMMC RX CMD/DATA Delay 2
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [17:16] stands for Rx Clock before Output Buffer
|
||||
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
|
||||
# [6:0] steps of delay for HS200, each 125ps.
|
||||
register "emmc_rx_cmd_data_cntl2" = "0x10008"
|
||||
|
||||
# Enable DPTF
|
||||
register "dptf_enable" = "1"
|
||||
|
||||
# PL1 override 12000 mW: the energy calculation is wrong with the
|
||||
# current VR solution. Experiments show that SoC TDP max (6W) can
|
||||
# be reached when RAPL PL1 is set to 12W.
|
||||
register "tdp_pl1_override_mw" = "12000"
|
||||
# Set RAPL PL2 to 15W.
|
||||
register "tdp_pl2_override_mw" = "15000"
|
||||
|
||||
# Enable Audio Clock and Power gating
|
||||
register "hdaudio_clk_gate_enable" = "1"
|
||||
register "hdaudio_pwr_gate_enable" = "1"
|
||||
register "hdaudio_bios_config_lockdown" = "1"
|
||||
|
||||
# Enable lpss s0ix
|
||||
register "lpss_s0ix_enable" = "1"
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route, i.e., if this route changes then the affected GPE
|
||||
# offset bits also need to be changed. This sets the PMC register
|
||||
# GPE_CFG fields.
|
||||
register "gpe0_dw1" = "PMC_GPE_N_31_0"
|
||||
register "gpe0_dw2" = "PMC_GPE_N_63_32"
|
||||
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
|
||||
|
||||
# Enable I2C0 for audio codec at 400kHz
|
||||
register "i2c[0]" = "{
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 104,
|
||||
.fall_time_ns = 52,
|
||||
}"
|
||||
|
||||
# Enable I2C2 bus early for TPM at 400kHz
|
||||
register "i2c[2]" = "{
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 50,
|
||||
.fall_time_ns = 23,
|
||||
}"
|
||||
|
||||
# touchscreen at 400kHz
|
||||
register "i2c[3]" = "{
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 76,
|
||||
.fall_time_ns = 164,
|
||||
}"
|
||||
|
||||
# trackpad at 400kHz
|
||||
register "i2c[4]" = "{
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 90,
|
||||
.fall_time_ns = 164,
|
||||
}"
|
||||
|
||||
# Minimum SLP S3 assertion width 28ms.
|
||||
register "slp_s3_assertion_width_usecs" = "28000"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # - Host Bridge
|
||||
device pci 00.1 on end # - DPTF
|
||||
device pci 00.2 on end # - NPK
|
||||
device pci 02.0 on end # - Gen
|
||||
device pci 03.0 on end # - Iunit
|
||||
device pci 0d.0 on end # - P2SB
|
||||
device pci 0d.1 on end # - PMC
|
||||
device pci 0d.2 on end # - SPI
|
||||
device pci 0d.3 on end # - Shared SRAM
|
||||
device pci 0e.0 on # - Audio
|
||||
chip drivers/generic/max98357a
|
||||
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
|
||||
register "sdmode_delay" = "5"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device pci 11.0 off end # - ISH
|
||||
device pci 12.0 off end # - SATA
|
||||
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
|
||||
device pci 13.1 off end # - Root Port 3 - PCIe-A 1
|
||||
device pci 13.2 off end # - Root Port 4 - PCIe-A 2
|
||||
device pci 13.3 off end # - Root Port 5 - PCIe-A 3
|
||||
device pci 14.0 on
|
||||
chip drivers/intel/wifi
|
||||
register "wake" = "GPE0_DW3_00"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end # - Root Port 0 - PCIe-B 0 - Wifi
|
||||
device pci 14.1 off end # - Root Port 1 - PCIe-B 1
|
||||
device pci 15.0 on end # - XHCI
|
||||
device pci 15.1 off end # - XDCI
|
||||
device pci 16.0 on # - I2C 0
|
||||
chip drivers/i2c/da7219
|
||||
register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)"
|
||||
register "btn_cfg" = "50"
|
||||
register "mic_det_thr" = "500"
|
||||
register "jack_ins_deb" = "20"
|
||||
register "jack_det_rate" = ""32ms_64ms""
|
||||
register "jack_rem_deb" = "1"
|
||||
register "a_d_btn_thr" = "0xa"
|
||||
register "d_b_btn_thr" = "0x16"
|
||||
register "b_c_btn_thr" = "0x21"
|
||||
register "c_mic_btn_thr" = "0x3e"
|
||||
register "btn_avg" = "4"
|
||||
register "adc_1bit_rpt" = "1"
|
||||
register "micbias_lvl" = "2600"
|
||||
register "mic_amp_in_sel" = ""diff""
|
||||
device i2c 1a on end
|
||||
end
|
||||
end
|
||||
device pci 16.1 on end # - I2C 1
|
||||
device pci 16.2 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end # - I2C 2
|
||||
device pci 16.3 on
|
||||
chip drivers/i2c/wacom
|
||||
register "generic" = "{
|
||||
.hid = WCOMNTN2_HID,
|
||||
.cid = PNP0C50_CID,
|
||||
.desc = WCOM_TS_DESC,
|
||||
.irq = IRQ_EDGE_LOW(GPIO_21_IRQ),
|
||||
.probed = 1,
|
||||
}"
|
||||
register "hid_desc_reg_offset" = "0x1"
|
||||
device i2c 0xA on end
|
||||
end
|
||||
end # - I2C 3
|
||||
device pci 17.0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)"
|
||||
register "wake" = "GPE0_DW1_15"
|
||||
register "probed" = "1"
|
||||
device i2c 15 on end
|
||||
end
|
||||
end # - I2C 4
|
||||
device pci 17.1 off end # - I2C 5
|
||||
device pci 17.2 off end # - I2C 6
|
||||
device pci 17.3 off end # - I2C 7
|
||||
device pci 18.0 on end # - UART 0
|
||||
device pci 18.1 on end # - UART 1
|
||||
device pci 18.2 on end # - UART 2
|
||||
device pci 18.3 off end # - UART 3
|
||||
device pci 19.0 on end # - SPI 0
|
||||
device pci 19.1 off end # - SPI 1
|
||||
device pci 19.2 off end # - SPI 2
|
||||
device pci 1a.0 on end # - PWM
|
||||
device pci 1b.0 on end # - SDCARD
|
||||
device pci 1c.0 on end # - eMMC
|
||||
device pci 1e.0 off end # - SDIO
|
||||
device pci 1f.0 on # - LPC
|
||||
chip ec/google/chromeec
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # - SMBUS
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define DPTF_CPU_PASSIVE 57
|
||||
#define DPTF_CPU_CRITICAL 90
|
||||
#define DPTF_CPU_ACTIVE_AC0 90
|
||||
#define DPTF_CPU_ACTIVE_AC1 80
|
||||
#define DPTF_CPU_ACTIVE_AC2 70
|
||||
#define DPTF_CPU_ACTIVE_AC3 60
|
||||
#define DPTF_CPU_ACTIVE_AC4 50
|
||||
|
||||
#define DPTF_TSR0_SENSOR_ID 0
|
||||
#define DPTF_TSR0_SENSOR_NAME "Battery"
|
||||
#define DPTF_TSR0_PASSIVE 48
|
||||
#define DPTF_TSR0_CRITICAL 70
|
||||
|
||||
#define DPTF_TSR1_SENSOR_ID 1
|
||||
#define DPTF_TSR1_SENSOR_NAME "Ambient"
|
||||
#define DPTF_TSR1_PASSIVE 55
|
||||
#define DPTF_TSR1_CRITICAL 70
|
||||
|
||||
#define DPTF_TSR2_SENSOR_ID 2
|
||||
#define DPTF_TSR2_SENSOR_NAME "Charger"
|
||||
#define DPTF_TSR2_PASSIVE 65
|
||||
#define DPTF_TSR2_CRITICAL 80
|
||||
|
||||
#define DPTF_ENABLE_CHARGER
|
||||
|
||||
/* Charger performance states, board-specific values from charger and EC */
|
||||
Name (CHPS, Package () {
|
||||
Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
|
||||
Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
|
||||
Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
|
||||
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
|
||||
Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
|
||||
})
|
||||
|
||||
Name (DTRT, Package () {
|
||||
/* CPU Throttle Effect on CPU */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 0 */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 500, 0, 0, 0, 0 },
|
||||
|
||||
#ifdef DPTF_ENABLE_CHARGER
|
||||
/* Charger Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
|
||||
#endif
|
||||
|
||||
/* CPU Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 550, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 2 */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 },
|
||||
})
|
||||
|
||||
Name (MPPC, Package ()
|
||||
{
|
||||
0x2, /* Revision */
|
||||
Package () { /* Power Limit 1 */
|
||||
0, /* PowerLimitIndex, 0 for Power Limit 1 */
|
||||
1600, /* PowerLimitMinimum */
|
||||
12000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
200 /* StepSize */
|
||||
},
|
||||
Package () { /* Power Limit 2 */
|
||||
1, /* PowerLimitIndex, 1 for Power Limit 2 */
|
||||
6000, /* PowerLimitMinimum */
|
||||
15000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
1000 /* StepSize */
|
||||
}
|
||||
})
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_EC_H
|
||||
#define MAINBOARD_EC_H
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#endif /* MAINBOARD_GPIO_H */
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
|
||||
static const struct lpddr4_sku skus[] = {
|
||||
/*
|
||||
* K4F6E304HB-MGCJ - both logical channels While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate
|
||||
* the deneisty as 8Gb per rank.
|
||||
*/
|
||||
[0] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "K4F6E304HB-MGCJ",
|
||||
},
|
||||
/* K4F8E304HB-MGCJ - both logical channels */
|
||||
[1] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "K4F8E304HB-MGCJ",
|
||||
},
|
||||
/*
|
||||
* MT53B512M32D2NP-062WT:C - both logical channels. While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate
|
||||
* the deneisty as 8Gb per rank.
|
||||
*/
|
||||
[2] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "MT53B512M32D2NP",
|
||||
.disable_periodic_retraining = 1,
|
||||
},
|
||||
/* MT53B256M32D1NP-062 WT:C - both logical channels */
|
||||
[3] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "MT53B256M32D1NP",
|
||||
.disable_periodic_retraining = 1,
|
||||
},
|
||||
/*
|
||||
* H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate the
|
||||
* density as 8Gb per rank.
|
||||
*/
|
||||
[4] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "H9HCNNNBPUMLHR",
|
||||
},
|
||||
/* H9HCNNN8KUMLHR-NLE - both logical channels */
|
||||
[5] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "H9HCNNN8KUMLHR",
|
||||
},
|
||||
/* Samsung 290 K4F6E304HB-MGCH 16Gb dual-ch */
|
||||
[0xe] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "K4F6E304HB-MGCH",
|
||||
},
|
||||
/* Samsung 280 K4F8E304HB-MGCH 8Gb dual-ch */
|
||||
[0xf] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 0,
|
||||
.ch1_dual_rank = 0,
|
||||
.part_num = "K4F8E304HB-MGCH",
|
||||
},
|
||||
};
|
||||
|
||||
static const struct lpddr4_cfg lp4cfg = {
|
||||
.skus = skus,
|
||||
.num_skus = ARRAY_SIZE(skus),
|
||||
.swizzle_config = &baseboard_lpddr4_swizzle,
|
||||
};
|
||||
|
||||
const struct lpddr4_cfg *variant_lpddr4_config(void)
|
||||
{
|
||||
return &lp4cfg;
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/acpi/dptf.asl>
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_EC_H
|
||||
#define MAINBOARD_EC_H
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#endif /* MAINBOARD_GPIO_H */
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
|
||||
# Disable unused clkreq of PCIe root ports
|
||||
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
|
||||
# GPIO for PERST_0
|
||||
# If the Board has PERST_0 signal, assign the GPIO
|
||||
# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
|
||||
register "prt0_gpio" = "GPIO_122"
|
||||
|
||||
# EMMC TX DATA Delay 1
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [14:8] steps of delay for HS400, each 125ps.
|
||||
# [6:0] steps of delay for SDR104/HS200, each 125ps.
|
||||
register "emmc_tx_data_cntl1" = "0x0C16"
|
||||
|
||||
# EMMC TX DATA Delay 2
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [30:24] steps of delay for SDR50, each 125ps.
|
||||
# [22:16] steps of delay for DDR50, each 125ps.
|
||||
# [14:8] steps of delay for SDR25/HS50, each 125ps.
|
||||
# [6:0] steps of delay for SDR12, each 125ps.
|
||||
register "emmc_tx_data_cntl2" = "0x28162828"
|
||||
|
||||
# EMMC RX CMD/DATA Delay 1
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [30:24] steps of delay for SDR50, each 125ps.
|
||||
# [22:16] steps of delay for DDR50, each 125ps.
|
||||
# [14:8] steps of delay for SDR25/HS50, each 125ps.
|
||||
# [6:0] steps of delay for SDR12, each 125ps.
|
||||
register "emmc_rx_cmd_data_cntl1" = "0x00181717"
|
||||
|
||||
# EMMC RX CMD/DATA Delay 2
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [17:16] stands for Rx Clock before Output Buffer
|
||||
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
|
||||
# [6:0] steps of delay for HS200, each 125ps.
|
||||
register "emmc_rx_cmd_data_cntl2" = "0x10008"
|
||||
|
||||
# Enable DPTF
|
||||
register "dptf_enable" = "1"
|
||||
|
||||
# PL1 override 12000 mW: the energy calculation is wrong with the
|
||||
# current VR solution. Experiments show that SoC TDP max (6W) can
|
||||
# be reached when RAPL PL1 is set to 12W.
|
||||
register "tdp_pl1_override_mw" = "12000"
|
||||
|
||||
# Enable Audio Clock and Power gating
|
||||
register "hdaudio_clk_gate_enable" = "1"
|
||||
register "hdaudio_pwr_gate_enable" = "1"
|
||||
register "hdaudio_bios_config_lockdown" = "1"
|
||||
|
||||
# Enable lpss s0ix
|
||||
register "lpss_s0ix_enable" = "1"
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route, i.e., if this route changes then the affected GPE
|
||||
# offset bits also need to be changed. This sets the PMC register
|
||||
# GPE_CFG fields.
|
||||
register "gpe0_dw1" = "PMC_GPE_N_31_0"
|
||||
register "gpe0_dw2" = "PMC_GPE_N_63_32"
|
||||
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
|
||||
|
||||
# Enable I2C0 for audio codec at 400kHz
|
||||
register "i2c[0]" = "{
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 44,
|
||||
.fall_time_ns = 22,
|
||||
}"
|
||||
|
||||
# Enable I2C2 bus early for TPM at 400kHz
|
||||
register "i2c[2]" = "{
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 40,
|
||||
.fall_time_ns = 20,
|
||||
}"
|
||||
|
||||
# touchscreen at 400kHz
|
||||
register "i2c[3]" = "{
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 70,
|
||||
.fall_time_ns = 164,
|
||||
}"
|
||||
|
||||
# trackpad at 400kHz
|
||||
register "i2c[4]" = "{
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 20,
|
||||
.fall_time_ns = 164,
|
||||
}"
|
||||
|
||||
# digitizer at 400kHz
|
||||
register "i2c[5]" = "{
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 152,
|
||||
.fall_time_ns = 30,
|
||||
}"
|
||||
|
||||
# Minimum SLP S3 assertion width 28ms.
|
||||
register "slp_s3_assertion_width_usecs" = "28000"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # - Host Bridge
|
||||
device pci 00.1 on end # - DPTF
|
||||
device pci 00.2 on end # - NPK
|
||||
device pci 02.0 on end # - Gen
|
||||
device pci 03.0 on end # - Iunit
|
||||
device pci 0d.0 on end # - P2SB
|
||||
device pci 0d.1 on end # - PMC
|
||||
device pci 0d.2 on end # - SPI
|
||||
device pci 0d.3 on end # - Shared SRAM
|
||||
device pci 0e.0 on # - Audio
|
||||
chip drivers/generic/max98357a
|
||||
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
|
||||
register "sdmode_delay" = "5"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device pci 11.0 off end # - ISH
|
||||
device pci 12.0 off end # - SATA
|
||||
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
|
||||
device pci 13.1 off end # - Root Port 3 - PCIe-A 1
|
||||
device pci 13.2 off end # - Root Port 4 - PCIe-A 2
|
||||
device pci 13.3 off end # - Root Port 5 - PCIe-A 3
|
||||
device pci 14.0 on
|
||||
chip drivers/intel/wifi
|
||||
register "wake" = "GPE0_DW3_00"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end # - Root Port 0 - PCIe-B 0 - Wifi
|
||||
device pci 14.1 off end # - Root Port 1 - PCIe-B 1
|
||||
device pci 15.0 on end # - XHCI
|
||||
device pci 15.1 off end # - XDCI
|
||||
device pci 16.0 on # - I2C 0
|
||||
chip drivers/i2c/da7219
|
||||
register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)"
|
||||
register "btn_cfg" = "50"
|
||||
register "mic_det_thr" = "500"
|
||||
register "jack_ins_deb" = "20"
|
||||
register "jack_det_rate" = ""32ms_64ms""
|
||||
register "jack_rem_deb" = "1"
|
||||
register "a_d_btn_thr" = "0xa"
|
||||
register "d_b_btn_thr" = "0x16"
|
||||
register "b_c_btn_thr" = "0x21"
|
||||
register "c_mic_btn_thr" = "0x3e"
|
||||
register "btn_avg" = "4"
|
||||
register "adc_1bit_rpt" = "1"
|
||||
register "micbias_lvl" = "2600"
|
||||
register "mic_amp_in_sel" = ""diff""
|
||||
device i2c 1a on end
|
||||
end
|
||||
end
|
||||
device pci 16.1 on end # - I2C 1
|
||||
device pci 16.2 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end # - I2C 2
|
||||
device pci 16.3 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0001""
|
||||
register "desc" = ""ELAN Touchscreen""
|
||||
register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)"
|
||||
register "probed" = "1"
|
||||
device i2c 10 on end
|
||||
end
|
||||
end # - I2C 3
|
||||
device pci 17.0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)"
|
||||
register "wake" = "GPE0_DW1_15"
|
||||
register "probed" = "1"
|
||||
device i2c 15 on end
|
||||
end
|
||||
end # - I2C 4
|
||||
device pci 17.1 on
|
||||
chip drivers/i2c/wacom
|
||||
register "generic" = "{
|
||||
.hid = WCOM50C1_HID,
|
||||
.cid = PNP0C50_CID,
|
||||
.desc = WCOM_DT_DESC,
|
||||
.irq = IRQ_LEVEL_LOW(GPIO_13_IRQ),
|
||||
}"
|
||||
register "hid_desc_reg_offset" = "0x1"
|
||||
device i2c 0x9 on end
|
||||
end
|
||||
end # - I2C 5
|
||||
device pci 17.2 on end # - I2C 6
|
||||
device pci 17.3 on end # - I2C 7
|
||||
device pci 18.0 on end # - UART 0
|
||||
device pci 18.1 on end # - UART 1
|
||||
device pci 18.2 on end # - UART 2
|
||||
device pci 18.3 on end # - UART 3
|
||||
device pci 19.0 on end # - SPI 0
|
||||
device pci 19.1 on end # - SPI 1
|
||||
device pci 19.2 on end # - SPI 2
|
||||
device pci 1a.0 on end # - PWM
|
||||
device pci 1b.0 on end # - SDCARD
|
||||
device pci 1c.0 on end # - eMMC
|
||||
device pci 1e.0 off end # - SDIO
|
||||
device pci 1f.0 on # - LPC
|
||||
chip ec/google/chromeec
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # - SMBUS
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define DPTF_CPU_PASSIVE 100
|
||||
#define DPTF_CPU_CRITICAL 105
|
||||
#define DPTF_CPU_ACTIVE_AC0 90
|
||||
#define DPTF_CPU_ACTIVE_AC1 80
|
||||
#define DPTF_CPU_ACTIVE_AC2 70
|
||||
#define DPTF_CPU_ACTIVE_AC3 60
|
||||
#define DPTF_CPU_ACTIVE_AC4 50
|
||||
|
||||
#define DPTF_TSR0_SENSOR_ID 0
|
||||
#define DPTF_TSR0_SENSOR_NAME "Battery"
|
||||
#define DPTF_TSR0_PASSIVE 48
|
||||
#define DPTF_TSR0_CRITICAL 70
|
||||
|
||||
#define DPTF_TSR1_SENSOR_ID 1
|
||||
#define DPTF_TSR1_SENSOR_NAME "Ambient"
|
||||
#define DPTF_TSR1_PASSIVE 53
|
||||
#define DPTF_TSR1_CRITICAL 80
|
||||
|
||||
#define DPTF_TSR2_SENSOR_ID 2
|
||||
#define DPTF_TSR2_SENSOR_NAME "Charger"
|
||||
#define DPTF_TSR2_PASSIVE 90
|
||||
#define DPTF_TSR2_CRITICAL 100
|
||||
|
||||
#define DPTF_ENABLE_CHARGER
|
||||
|
||||
/* Charger performance states, board-specific values from charger and EC */
|
||||
Name (CHPS, Package () {
|
||||
Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
|
||||
Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
|
||||
Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
|
||||
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
|
||||
Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
|
||||
})
|
||||
|
||||
Name (DTRT, Package () {
|
||||
/* CPU Throttle Effect on CPU */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 0 */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
|
||||
|
||||
#ifdef DPTF_ENABLE_CHARGER
|
||||
/* Charger Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 },
|
||||
#endif
|
||||
|
||||
/* CPU Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 200, 80, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 2 */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 150, 0, 0, 0, 0 },
|
||||
})
|
||||
|
||||
Name (MPPC, Package ()
|
||||
{
|
||||
0x2, /* Revision */
|
||||
Package () { /* Power Limit 1 */
|
||||
0, /* PowerLimitIndex, 0 for Power Limit 1 */
|
||||
4000, /* PowerLimitMinimum */
|
||||
12000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
200 /* StepSize */
|
||||
},
|
||||
Package () { /* Power Limit 2 */
|
||||
1, /* PowerLimitIndex, 1 for Power Limit 2 */
|
||||
8000, /* PowerLimitMinimum */
|
||||
8000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
1000 /* StepSize */
|
||||
}
|
||||
})
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_EC_H
|
||||
#define MAINBOARD_EC_H
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#endif /* MAINBOARD_GPIO_H */
|
||||
Loading…
Reference in New Issue