intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI

This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI
in preparation to allow V1 and V2 versions of MP services PPI.

TEST=Verified that timeless build for brya, volteer, icelake_rvp,
elkhartlake_crb and waddledee shows no change in generated coreboot.rom

Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50275
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/x86/cpu.c

@@ -334,7 +334,7 @@ void arch_bootstate_coreboot_exit(void)
  * function will always getting called from coreboot context
  * (ESP stack pointer will always refer to coreboot).
  *
- * But with FSP_USES_MP_SERVICES_PPI implementation in coreboot this
+ * But with MP_SERVICES_PPI implementation in coreboot this
  * assumption might not be true, where FSP context (stack pointer refers
  * to FSP) will request to get cpu_index().
  *

src/arch/x86/include/arch/cpu.h

@@ -306,7 +306,7 @@ uint32_t cpu_get_feature_flags_edx(void);
  * function will always getting called from coreboot context
  * (ESP stack pointer will always refer to coreboot).
  *
- * But with FSP_USES_MP_SERVICES_PPI implementation in coreboot this
+ * But with MP_SERVICES_PPI implementation in coreboot this
  * assumption might not be true, where FSP context (stack pointer refers
  * to FSP) will request to get cpu_index().
  *

src/drivers/intel/fsp2_0/ppi/Kconfig

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-config FSP_USES_MP_SERVICES_PPI
+config MP_SERVICES_PPI
 	bool
 	default n
 	depends on SOC_INTEL_COMMON_BLOCK_CPU_MPINIT

src/drivers/intel/fsp2_0/ppi/Makefile.inc

@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-ramstage-$(CONFIG_FSP_USES_MP_SERVICES_PPI) += mp_service_ppi.c
+ramstage-$(CONFIG_MP_SERVICES_PPI) += mp_service_ppi.c

src/soc/intel/alderlake/Kconfig

@@ -34,12 +34,12 @@ config CPU_SPECIFIC_OPTIONS
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select IOAPIC
 	select INTEL_TME
+	select MP_SERVICES_PPI
 	select MRC_SETTINGS_PROTECT
 	select PARALLEL_MP
 	select PARALLEL_MP_AP_WORK
 	select MICROCODE_BLOB_UNDISCLOSED
 	select PLATFORM_USES_FSP2_2
-	select FSP_USES_MP_SERVICES_PPI
 	select REG_SCRIPT
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select PMC_LOW_POWER_MODE_PROGRAM

src/soc/intel/common/block/cpu/Kconfig

@@ -75,7 +75,7 @@ config USE_INTEL_FSP_MP_INIT
 
 config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
 	bool "Perform MP Initialization by FSP using coreboot MP PPI service"
-	default y if FSP_USES_MP_SERVICES_PPI
+	default y if MP_SERVICES_PPI
 	default n
 	help
 	  This option allows FSP to make use of MP services PPI published by

src/soc/intel/elkhartlake/Kconfig

@@ -26,12 +26,12 @@ config CPU_SPECIFIC_OPTIONS
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select IOAPIC
+	select MP_SERVICES_PPI
 	select MRC_SETTINGS_PROTECT
 	select PARALLEL_MP
 	select PARALLEL_MP_AP_WORK
 	select MICROCODE_BLOB_UNDISCLOSED
 	select PLATFORM_USES_FSP2_1
-	select FSP_USES_MP_SERVICES_PPI
 	select REG_SCRIPT
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select PMC_LOW_POWER_MODE_PROGRAM

src/soc/intel/icelake/Kconfig

@@ -26,12 +26,12 @@ config CPU_SPECIFIC_OPTIONS
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select IOAPIC
+	select MP_SERVICES_PPI
 	select MRC_SETTINGS_PROTECT
 	select PARALLEL_MP
 	select PARALLEL_MP_AP_WORK
 	select MICROCODE_BLOB_UNDISCLOSED
 	select PLATFORM_USES_FSP2_1
-	select FSP_USES_MP_SERVICES_PPI
 	select REG_SCRIPT
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select PMC_LOW_POWER_MODE_PROGRAM

src/soc/intel/jasperlake/Kconfig

@@ -27,12 +27,12 @@ config CPU_SPECIFIC_OPTIONS
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select IOAPIC
+	select MP_SERVICES_PPI
 	select MRC_SETTINGS_PROTECT
 	select PARALLEL_MP
 	select PARALLEL_MP_AP_WORK
 	select MICROCODE_BLOB_UNDISCLOSED
 	select PLATFORM_USES_FSP2_2
-	select FSP_USES_MP_SERVICES_PPI
 	select REG_SCRIPT
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select PMC_LOW_POWER_MODE_PROGRAM

src/soc/intel/tigerlake/Kconfig

@@ -30,12 +30,12 @@ config CPU_SPECIFIC_OPTIONS
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select IOAPIC
+	select MP_SERVICES_PPI
 	select MRC_SETTINGS_PROTECT
 	select PARALLEL_MP
 	select PARALLEL_MP_AP_WORK
 	select MICROCODE_BLOB_UNDISCLOSED
 	select PLATFORM_USES_FSP2_2
-	select FSP_USES_MP_SERVICES_PPI
 	select REG_SCRIPT
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select PMC_LOW_POWER_MODE_PROGRAM