diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl
index 04e41a1b57..12480c7d0f 100644
--- a/src/soc/amd/picasso/acpi/globalnvs.asl
+++ b/src/soc/amd/picasso/acpi/globalnvs.asl
@@ -55,9 +55,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	, 1,
 	UT0E,	1,	//        UART0, 11
 	UT1E,	1,	//        UART1, 12
-	, 2,
-	ST_E,	1,	//        SATA, 15
-	, 11,
+	, 14,
 	ESPI,	1,	//        ESPI, 27
 	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
 	Offset (0x100),
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
index 645d55569e..5e16fefaa5 100644
--- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
@@ -236,13 +236,6 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
 	offset (0x1e59), /* UART1 D3 State */
 	U1DS, 3,
 
-	offset (0x1e5e), /* SATA D3 Control */
-	SATD, 2,
-	, 1,
-	SAPD, 1,
-	offset (0x1e5f), /* SATA D3 State */
-	SADS, 3,
-
 	offset (0x1e71), /* SD D3 State */
 	SDDS, 3,
 
@@ -315,7 +308,7 @@ Field(FCFG, DwordAcc, NoLock, Preserve)
 /*
  * Arg0:device:
  *  5=I2C0, 6=I2C1, 7=I2C2, 8=I2C3, 11=UART0, 12=UART1,
- *  15=SATA, 18=EHCI, 23=xHCI, 24=SD
+ *  18=EHCI, 23=xHCI, 24=SD
  * Arg1:D-state
  */
 Mutex (FDAS, 0) /* FCH Device AOAC Semophore */
@@ -382,7 +375,6 @@ Method(FDDC, 2, Serialized)
 					Store(U1DS, Local0)
 				}
 			}
-/* todo			Case(15) { STD0()} */ /* SATA */
 		}
 	} else {
 		/* put device into D3cold */
@@ -435,7 +427,6 @@ Method(FDDC, 2, Serialized)
 				}
 				Store(0x03, U1TD)
 			}
-/* todo			Case(15) { STD3()} */ /* SATA */
 		}
 		if(LEqual(I1TD, 3)) {
 			if(LEqual(I2TD, 3)) {
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 96892cc542..8bd061b2fc 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -294,9 +294,7 @@ typedef struct aoac_devs {
 	unsigned int :1;
 	unsigned int ut0e:1; /* 11: UART0 */
 	unsigned int ut1e:1; /* 12: UART1 */
-	unsigned int :2;
-	unsigned int st_e:1; /* 15: SATA */
-	unsigned int :11;
+	unsigned int :14;
 	unsigned int espi:1; /* 27: ESPI */
 	unsigned int :4;
 } __packed aoac_devs_t;
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index ec7b76f749..92067286a9 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -454,8 +454,6 @@ void southbridge_init(void *chip_info)
 
 static void set_sb_final_nvs(void)
 {
-	const struct device *sata;
-
 	struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 	if (gnvs == NULL)
 		return;
@@ -465,9 +463,6 @@ static void set_sb_final_nvs(void)
 	gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C4);
 	gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0);
 	gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1);
-	/* Rely on these being in sync with devicetree */
-	sata = pcidev_path_on_root(SATA_DEVFN);
-	gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0;
 	gnvs->aoac.espi = 1;
 }