Fix multiple missing files and errors from the recent commit. This happened
when Patrick's tree and mine got out of sync. Link stage still fails. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
9a94843820
commit
5f6572ec8b
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@ -458,7 +458,12 @@ obj-$(CONFIG_HAVE_ACPI_TABLES) += amdk8_acpi.o
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\subsection{southbridge}
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\subsubsection{vendor and part}
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\subsection{superio}
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\subsection{i2cmux}
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\subsection{drivers/i2c}
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This is a rather special case. There are no Kconfig files or Makefile.inc files here. They are notneeed.
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To compile in one of these files, name the .o directory. E.g. in serengeti_cheetah we have:
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\begin{verbatim}
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\end{verbatim}
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\subsubsection{vendor and part}
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\end{document}
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@ -1,4 +1,4 @@
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#source src/cpu/amd/Kconfig
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source src/cpu/amd/Kconfig
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source src/cpu/emulation/Kconfig
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source src/cpu/intel/Kconfig
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source src/cpu/via/Kconfig
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@ -16,3 +16,7 @@ config DCACHE_RAM_SIZE
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config SMP
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bool
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default n
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config CPU_SOCKET_TYPE
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hex
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default 0
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@ -1,8 +1,8 @@
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source src/cpu/amd/socket_754/Kconfig
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source src/cpu/amd/socket_939/Kconfig
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source src/cpu/amd/socket_940/Kconfig
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source src/cpu/amd/socket_AM2/Kconfig
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source src/cpu/amd/socket_AM2r2/Kconfig
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#source src/cpu/amd/socket_754/Kconfig
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#source src/cpu/amd/socket_939/Kconfig
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#source src/cpu/amd/socket_940/Kconfig
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#source src/cpu/amd/socket_AM2/Kconfig
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#source src/cpu/amd/socket_AM2r2/Kconfig
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source src/cpu/amd/socket_F/Kconfig
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source src/cpu/amd/socket_F_1207/Kconfig
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source src/cpu/amd/socket_S1G1/Kconfig
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#source src/cpu/amd/socket_F_1207/Kconfig
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#source src/cpu/amd/socket_S1G1/Kconfig
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@ -0,0 +1,13 @@
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config HAVE_INIT_TIMER
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int
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default 1
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config HAVE_MOVNTI
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int
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default 1
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config CPU_ADDR_BITS
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int
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default 40
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@ -1,3 +1,32 @@
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config CPU_AMD_SOCKET_F
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bool
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default false
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config CPU_SOCKET_TYPE
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hex
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default 0x10
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depends on CPU_AMD_SOCKET_F
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config K8_REV_F_SUPPORT
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hex
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default 1
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depends on CPU_AMD_SOCKET_F
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#Opteron K8 1G HT Support
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config K8_HT_FREQ_1G_SUPPORT
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hex
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default 1
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depends on CPU_AMD_SOCKET_F
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#DDR2 and REG
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config DIMM_SUPPORT
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hex
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default 0x0104
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depends on CPU_AMD_SOCKET_F
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config CPU_SOCKET_TYPE
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hex
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default 0x10
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depends on CPU_AMD_SOCKET_F
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source src/cpu/amd/model_fxx/Kconfig
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@ -10,9 +10,9 @@ config BOARD_AMD_SERENGETI_CHEETAH
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select NORTHBRIDGE_AMD_AMDK8
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select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
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select SOUTHBRIDGE_AMD_AMD8111
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select SUPERIO_WINBOND_W83627THF
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select SOUTHBRIDGE_AMD_AMD8131
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select SUPERIO_WINBOND_W83627HF
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select PIRQ_TABLE
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select MMCONF_SUPPORT
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select USE_PRINTK_IN_CAR
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help
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AMD Serengeti Series mainboards
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@ -23,15 +23,45 @@ config MAINBOARD_DIR
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default amd/serengeti_cheetah
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depends on BOARD_AMD_SERENGETI_CHEETAH
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#config DCACHE_RAM_BASE
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# hex
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# default 0xffdf8000
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# depends on BOARD_AMD_SERENGETI_CHEETAH
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#
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#config DCACHE_RAM_SIZE
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# hex
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# default 0x8000
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# depends on BOARD_AMD_SERENGETI_CHEETAH
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config USE_DCACHE_RAM
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int
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default 1
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config DCACHE_RAM_SIZE
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hex
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default 0x08000
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x01000
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config APIC_ID_OFFSET
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int
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default 8
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config HAVE_HARD_RESET
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int
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default 1
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config IOAPIC
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int
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default 1
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config LB_CKS_RANGE_END
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int
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@ -47,3 +77,119 @@ config MAINBOARD_PART_NUMBER
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string
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default "Serengeti-Cheetah"
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config PCI_64BIT_PREF_MEM
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int
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default 0
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config USE_DCACHE_RAM
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int
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default 1
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config DCACHE_RAM_SIZE
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hex
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default 0x08000
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x01000
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config USE_FAILOVER_IMAGE
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int
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default 0
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config MEM_TRAIN_SEQ
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int
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default 1
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config HAVE_FAILOVER_BOOT
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int
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default 0
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config USE_FAILOVER_IMAGE
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int
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default 0
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config MAX_CPUS
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int
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default 8
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config MAX_PHYSICAL_CPUS
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int
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default 4
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config MEM_TRAIN_SEQ
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int
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default 1
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config AP_CODE_IN_CAR
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int
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default 1
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config HW_MEM_HOLE_SIZE_AUTO_INC
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int
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default 0
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config HT_CHAIN_END_UNITID_BASE
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int
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default 0x6
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config USE_INIT
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int
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default 0
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config SERIAL_CPU_INIT
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int
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default 0
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config AP_CODE_IN_CAR
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int
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default 1
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config WAIT_BEFORE_CPUS_INIT
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int
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default 1
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config CONSOLE_VGA
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bool
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default y
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config PCI_ROM_RUN
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int
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default 1
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depends on BOARD_AMD_SERENGETI_CHEETAH
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@ -37,6 +37,7 @@ obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
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obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o
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obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o
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obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt4.o
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driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o
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# This is part of the conversion to init-obj and away from included code.
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@ -58,11 +59,9 @@ ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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ifdef POST_EVALUATION
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MAINBOARD_OPTIONS=\
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-DCONFIG_AP_IN_SIPI_WAIT=1 \
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-DCONFIG_AP_IN_SIPI_WAIT=0 \
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-DCONFIG_USE_PRINTK_IN_CAR=1 \
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-DCONFIG_HAVE_HIGH_TABLES=1 \
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-DCONFIG_MMCONF_SUPPORT=1 \
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-DCONFIG_MMCONF_BASE_ADDRESS=0xf0000000
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-DCONFIG_HAVE_HIGH_TABLES=1
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$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
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iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
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@ -86,8 +85,8 @@ $(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
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perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
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mv pci4.hex ssdt4.c
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$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
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$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
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$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/rom.c $(obj)/option_table.h
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$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/rom.c -o $@
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perl -e 's/\.rodata/.rom.data/g' -pi $@
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perl -e 's/\.text/.section .rom.text/g' -pi $@
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@ -0,0 +1,398 @@
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#define ASSEMBLY 1
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#define __ROMCC__
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#define RAMINIT_SYSINFO 1
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#define CACHE_AS_RAM_ADDRESS_DEBUG 0
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#define SET_NB_CFG_54 1
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//used by raminit
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#define QRANK_DIMM_SUPPORT 1
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//used by incoherent_ht
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//#define K8_SCAN_PCI_BUS 1
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//#define K8_ALLOCATE_IO_RANGE 1
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//used by init_cpus and fidvid
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#define K8_SET_FIDVID 0
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//if we want to wait for core1 done before DQS training, set it to 0
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#define K8_SET_FIDVID_CORE0_ONLY 1
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#if CONFIG_K8_REV_F_SUPPORT == 1
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#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
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#endif
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#include <stdint.h>
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#include <string.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#if 0
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static void post_code(uint8_t value) {
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#if 1
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int i;
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for(i=0;i<0x80000;i++) {
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outb(value, 0x80);
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}
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#endif
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}
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#endif
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#if CONFIG_USE_FAILOVER_IMAGE==0
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include <cpu/amd/model_fxx_rev.h>
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/amd/model_fxx/apic_timer.c"
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#endif
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#if CONFIG_USE_FAILOVER_IMAGE==0
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#include "cpu/x86/bist.h"
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#include "lib/delay.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include "cpu/amd/mtrr/amd_earlymtrr.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
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static void memreset_setup(void)
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{
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//GPIO on amd8111 to enable MEMRST ????
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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#define SMBUS_HUB 0x18
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int ret,i;
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unsigned device=(ctrl->channel0[0])>>8;
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/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
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i=2;
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do {
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ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
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} while ((ret!=0) && (i-->0));
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smbus_write_byte(SMBUS_HUB, 0x03, 0);
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}
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#if 0
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static inline void change_i2c_mux(unsigned device)
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{
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#define SMBUS_HUB 0x18
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int ret, i;
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print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
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i=2;
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do {
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ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
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print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
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} while ((ret!=0) && (i-->0));
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ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
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print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
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}
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#endif
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/amdk8/amdk8.h"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "northbridge/amd/amdk8/raminit_f.c"
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#include "sdram/generic_sdram.c"
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/* tyan does not want the default */
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#include "resourcemap.c"
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#include "cpu/amd/dualcore/dualcore.c"
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#define RC0 ((1<<0)<<8)
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#define RC1 ((1<<1)<<8)
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#define RC2 ((1<<2)<<8)
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#define RC3 ((1<<3)<<8)
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#define DIMM0 0x50
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#define DIMM1 0x51
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#define DIMM2 0x52
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#define DIMM3 0x53
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#define DIMM4 0x54
|
||||
#define DIMM5 0x55
|
||||
#define DIMM6 0x56
|
||||
#define DIMM7 0x57
|
||||
|
||||
|
||||
#include "cpu/amd/car/copy_and_run.c"
|
||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
|
||||
#include "cpu/amd/model_fxx/fidvid.c"
|
||||
#endif
|
||||
|
||||
#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
|
||||
|
||||
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
|
||||
unsigned last_boot_normal_x = last_boot_normal();
|
||||
|
||||
/* Is this a cpu only reset? or Is this a secondary cpu? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* Setup the rom access for 4M */
|
||||
amd8111_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the bios */
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
);
|
||||
|
||||
fallback_image:
|
||||
#if CONFIG_HAVE_FAILOVER_BOOT==1
|
||||
__asm__ volatile ("jmp __fallback_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
)
|
||||
#endif
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
#if CONFIG_HAVE_FAILOVER_BOOT==1
|
||||
#if CONFIG_USE_FAILOVER_IMAGE==1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#else
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
#else
|
||||
#if CONFIG_USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if CONFIG_USE_FAILOVER_IMAGE==0
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const uint16_t spd_addr[] = {
|
||||
//first node
|
||||
RC0|DIMM0, RC0|DIMM2, 0, 0,
|
||||
RC0|DIMM1, RC0|DIMM3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
//second node
|
||||
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
|
||||
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 2
|
||||
// third node
|
||||
RC2|DIMM0, RC2|DIMM2, 0, 0,
|
||||
RC2|DIMM1, RC2|DIMM3, 0, 0,
|
||||
// four node
|
||||
RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
|
||||
RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
|
||||
int needs_reset; int i;
|
||||
unsigned bsp_apicid = 0;
|
||||
struct cpuid_result cpuid1;
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
}
|
||||
|
||||
// post_code(0x32);
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
|
||||
|
||||
setup_mb_resource_map();
|
||||
#if 0
|
||||
dump_pci_device(PCI_DEV(0, 0x18, 0));
|
||||
dump_pci_device(PCI_DEV(0, 0x19, 0));
|
||||
#endif
|
||||
|
||||
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
|
||||
|
||||
#if CONFIG_MEM_TRAIN_SEQ == 1
|
||||
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
|
||||
#endif
|
||||
setup_coherent_ht_domain(); // routing table and start other core0
|
||||
|
||||
wait_all_core0_started();
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
|
||||
* So here need to make sure last core0 is started, esp for two way system,
|
||||
* (there may be apic id conflicts in that case)
|
||||
*/
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
/* it will set up chains and store link pair for optimization later */
|
||||
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
|
||||
|
||||
#if 0
|
||||
//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
|
||||
needs_reset = optimize_link_coherent_ht();
|
||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
||||
#endif
|
||||
|
||||
#if K8_SET_FIDVID == 1
|
||||
/* Check to see if processor is capable of changing FIDVID */
|
||||
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
|
||||
cpuid1 = cpuid(0x80000007);
|
||||
if( (cpuid1.edx & 0x6) == 0x6 ) {
|
||||
|
||||
{
|
||||
/* Read FIDVID_STATUS */
|
||||
msr_t msr;
|
||||
msr=rdmsr(0xc0010042);
|
||||
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
|
||||
|
||||
}
|
||||
|
||||
enable_fid_change();
|
||||
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
|
||||
init_fidvid_bsp(bsp_apicid);
|
||||
|
||||
// show final fid and vid
|
||||
{
|
||||
msr_t msr;
|
||||
msr=rdmsr(0xc0010042);
|
||||
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
|
||||
|
||||
}
|
||||
|
||||
} else {
|
||||
print_debug("Changing FIDVID not supported\n");
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
needs_reset = optimize_link_coherent_ht();
|
||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
||||
|
||||
// fidvid change will issue one LDTSTOP and the HT change will be effective too
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
}
|
||||
#endif
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
//It's the time to set ctrl in sysinfo now;
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
enable_smbus();
|
||||
|
||||
#if 0
|
||||
for(i=0;i<4;i++) {
|
||||
activate_spd_rom(&cpu[i]);
|
||||
dump_smbus_registers();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
for(i=1;i<256;i<<=1) {
|
||||
change_i2c_mux(i);
|
||||
dump_smbus_registers();
|
||||
}
|
||||
#endif
|
||||
|
||||
memreset_setup();
|
||||
|
||||
//do we need apci timer, tsc...., only debug need it for better output
|
||||
/* all ap stopped? */
|
||||
// init_timer(); // Need to use TMICT to synconize FID/VID
|
||||
|
||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||
|
||||
#if 0
|
||||
print_pci_devices();
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
// dump_pci_devices();
|
||||
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
|
||||
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
|
||||
#endif
|
||||
|
||||
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
|
||||
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue