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mb/google/reef: Disable unused devices in devicetrees 

The image processing unit (Iunit) and SoC UARTS are not used on any
reef boards.

Change-Id: Iacdf93b4952cbc63fc465f07d440463106527b8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Matt DeVillier 2022-02-13 13:20:17 -06:00 committed by Matt DeVillier
parent d095fd8cf1
commit 5f662e9f75
5 changed files with 7 additions and 7 deletions
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2
src/mainboard/google/reef/variants/baseboard/devicetree.cb
View File

@ -124,7 +124,7 @@ chip soc/intel/apollolake
device pci 02.0 on # - Gen device pci 02.0 on # - Gen
register "gfx" = "GMA_DEFAULT_PANEL(0)" register "gfx" = "GMA_DEFAULT_PANEL(0)"
end end
device pci 03.0 on end # - Iunit device pci 03.0 off end # - Iunit
device pci 0d.0 on end # - P2SB device pci 0d.0 on end # - P2SB
device pci 0d.1 on end # - PMC device pci 0d.1 on end # - PMC
device pci 0d.2 on end # - SPI device pci 0d.2 on end # - SPI

6
src/mainboard/google/reef/variants/coral/devicetree.cb
View File

@ -124,7 +124,7 @@ chip soc/intel/apollolake
device pci 02.0 on # - Gen device pci 02.0 on # - Gen
register "gfx" = "GMA_DEFAULT_PANEL(0)" register "gfx" = "GMA_DEFAULT_PANEL(0)"
end end
device pci 03.0 on end # - Iunit device pci 03.0 off end # - Iunit
device pci 0d.0 on end # - P2SB device pci 0d.0 on end # - P2SB
device pci 0d.1 on end # - PMC device pci 0d.1 on end # - PMC
device pci 0d.2 on end # - SPI device pci 0d.2 on end # - SPI
@ -238,8 +238,8 @@ chip soc/intel/apollolake
device pci 17.2 off end # - I2C 6 device pci 17.2 off end # - I2C 6
device pci 17.3 off end # - I2C 7 device pci 17.3 off end # - I2C 7
device pci 18.0 on end # - UART 0 device pci 18.0 on end # - UART 0
device pci 18.1 on end # - UART 1 device pci 18.1 off end # - UART 1
device pci 18.2 on end # - UART 2 device pci 18.2 off end # - UART 2
device pci 18.3 off end # - UART 3 device pci 18.3 off end # - UART 3
device pci 19.0 on end # - SPI 0 device pci 19.0 on end # - SPI 0
device pci 19.1 off end # - SPI 1 device pci 19.1 off end # - SPI 1

2
src/mainboard/google/reef/variants/pyro/devicetree.cb
View File

@ -133,7 +133,7 @@ chip soc/intel/apollolake
device pci 02.0 on # - Gen device pci 02.0 on # - Gen
register "gfx" = "GMA_DEFAULT_PANEL(0)" register "gfx" = "GMA_DEFAULT_PANEL(0)"
end end
device pci 03.0 on end # - Iunit device pci 03.0 off end # - Iunit
device pci 0d.0 on end # - P2SB device pci 0d.0 on end # - P2SB
device pci 0d.1 on end # - PMC device pci 0d.1 on end # - PMC
device pci 0d.2 on end # - SPI device pci 0d.2 on end # - SPI

2
src/mainboard/google/reef/variants/sand/devicetree.cb
View File

@ -120,7 +120,7 @@ chip soc/intel/apollolake
device pci 02.0 on # - Gen device pci 02.0 on # - Gen
register "gfx" = "GMA_DEFAULT_PANEL(0)" register "gfx" = "GMA_DEFAULT_PANEL(0)"
end end
device pci 03.0 on end # - Iunit device pci 03.0 off end # - Iunit
device pci 0d.0 on end # - P2SB device pci 0d.0 on end # - P2SB
device pci 0d.1 on end # - PMC device pci 0d.1 on end # - PMC
device pci 0d.2 on end # - SPI device pci 0d.2 on end # - SPI

2
src/mainboard/google/reef/variants/snappy/devicetree.cb
View File

@ -129,7 +129,7 @@ chip soc/intel/apollolake
device pci 02.0 on # - Gen device pci 02.0 on # - Gen
register "gfx" = "GMA_DEFAULT_PANEL(0)" register "gfx" = "GMA_DEFAULT_PANEL(0)"
end end
device pci 03.0 on end # - Iunit device pci 03.0 off end # - Iunit
device pci 0d.0 on end # - P2SB device pci 0d.0 on end # - P2SB
device pci 0d.1 on end # - PMC device pci 0d.1 on end # - PMC
device pci 0d.2 on end # - SPI device pci 0d.2 on end # - SPI