soc/amd/picasso: Change header guards from stoney to picasso
TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I32b7dbeae7538884311ccfc3a0e8db63c48fe356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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@ -13,8 +13,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __STONEYRIDGE_CHIP_H__
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#define __STONEYRIDGE_CHIP_H__
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#ifndef __PICASSO_CHIP_H__
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#define __PICASSO_CHIP_H__
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#include <stddef.h>
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#include <stdint.h>
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@ -78,4 +78,4 @@ typedef struct soc_amd_stoneyridge_config config_t;
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extern struct device_operations pci_domain_ops;
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#endif /* __STONEYRIDGE_CHIP_H__ */
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#endif /* __PICASSO_CHIP_H__ */
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@ -15,8 +15,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __SOC_STONEYRIDGE_ACPI_H__
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#define __SOC_STONEYRIDGE_ACPI_H__
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#ifndef __SOC_PICASSO_ACPI_H__
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#define __SOC_PICASSO_ACPI_H__
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#include <arch/acpi.h>
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@ -37,4 +37,4 @@ void southbridge_inject_dsdt(struct device *device);
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const char *soc_acpi_name(const struct device *dev);
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#endif /* __SOC_STONEYRIDGE_ACPI_H__ */
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#endif /* __SOC_PICASSO_ACPI_H__ */
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@ -13,8 +13,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __STONEYRIDGE_CPU_H__
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#define __STONEYRIDGE_CPU_H__
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#ifndef __PICASSO_CPU_H__
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#define __PICASSO_CPU_H__
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#include <device/device.h>
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@ -32,4 +32,4 @@
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void stoney_init_cpus(struct device *dev);
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void check_mca(void);
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#endif /* __STONEYRIDGE_CPU_H__ */
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#endif /* __PICASSO_CPU_H__ */
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@ -13,8 +13,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __STONEYRIDGE_GPIO_H__
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#define __STONEYRIDGE_GPIO_H__
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#ifndef __PICASSO_GPIO_H__
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#define __PICASSO_GPIO_H__
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#define GPIO_DEVICE_NAME "AMD0030"
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#define GPIO_DEVICE_DESC "GPIO Controller"
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@ -305,4 +305,4 @@
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#define GPIO_2_EVENT GEVENT_8
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#endif /* __ACPI__ */
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#endif /* __STONEYRIDGE_GPIO_H__ */
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#endif /* __PICASSO_GPIO_H__ */
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@ -13,8 +13,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __STONEYRIDGE_I2C_H__
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#define __STONEYRIDGE_I2C_H__
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#ifndef __PICASSO_I2C_H__
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#define __PICASSO_I2C_H__
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#include <soc/gpio.h>
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@ -46,4 +46,4 @@ struct soc_amd_i2c_save {
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void sb_reset_i2c_slaves(void);
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#endif /* __STONEYRIDGE_I2C_H__ */
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#endif /* __PICASSO_I2C_H__ */
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@ -14,8 +14,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __SOC_STONEYRIDGE_IOMAP_H__
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#define __SOC_STONEYRIDGE_IOMAP_H__
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#ifndef __SOC_PICASSO_IOMAP_H__
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#define __SOC_PICASSO_IOMAP_H__
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/* MMIO Ranges */
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#define PSP_MAILBOX_BAR3_BASE 0xf0a00000
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@ -85,4 +85,4 @@
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#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */
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#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
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#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */
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#endif /* __SOC_PICASSO_IOMAP_H__ */
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@ -14,8 +14,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__
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#define __PI_STONEYRIDGE_NORTHBRIDGE_H__
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#ifndef __PI_PICASSO_NORTHBRIDGE_H__
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#define __PI_PICASSO_NORTHBRIDGE_H__
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#include <device/device.h>
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#include <types.h>
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@ -130,4 +130,4 @@ void set_ap_entry_ptr(void *entry);
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void set_warm_reset_flag(void);
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int is_warm_reset(void);
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#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */
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#endif /* __PI_PICASSO_NORTHBRIDGE_H__ */
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@ -21,8 +21,8 @@
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*
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*/
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#ifndef __SOC_STONEYRIDGE_NVS_H__
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#define __SOC_STONEYRIDGE_NVS_H__
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#ifndef __SOC_PICASSO_NVS_H__
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#define __SOC_PICASSO_NVS_H__
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#include <commonlib/helpers.h>
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#include <stdint.h>
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@ -64,4 +64,4 @@ typedef struct global_nvs_t {
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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#endif /* __SOC_STONEYRIDGE_NVS_H__ */
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#endif /* __SOC_PICASSO_NVS_H__ */
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@ -13,8 +13,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__
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#define __PI_STONEYRIDGE_PCI_DEVS_H__
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#ifndef __PI_PICASSO_PCI_DEVS_H__
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#define __PI_PICASSO_PCI_DEVS_H__
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#include <device/pci_def.h>
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@ -195,4 +195,4 @@
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#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC)
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#define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC)
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#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */
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#endif /* __PI_PICASSO_PCI_DEVS_H__ */
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@ -13,9 +13,9 @@
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* GNU General Public License for more details.
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*/
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#ifndef __STONEYRIDGE_ROMSTAGE_H__
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#define __STONEYRIDGE_ROMSTAGE_H__
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#ifndef __PICASSO_ROMSTAGE_H__
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#define __PICASSO_ROMSTAGE_H__
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void mainboard_romstage_entry(int s3_resume);
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#endif /* __STONEYRIDGE_ROMSTAGE_H__ */
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#endif /* __PICASSO_ROMSTAGE_H__ */
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@ -13,8 +13,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __STONEYRIDGE_SMBUS_H__
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#define __STONEYRIDGE_SMBUS_H__
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#ifndef __PICASSO_SMBUS_H__
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#define __PICASSO_SMBUS_H__
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#include <stdint.h>
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#include <soc/iomap.h>
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@ -32,4 +32,4 @@ int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val);
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int do_smbus_recv_byte(u32 mmio, u8 device);
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int do_smbus_send_byte(u32 mmio, u8 device, u8 val);
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#endif /* __STONEYRIDGE_SMBUS_H__ */
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#endif /* __PICASSO_SMBUS_H__ */
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@ -15,8 +15,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
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#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
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#ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__
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#define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__
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#define SMI_GEVENTS 24
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@ -239,4 +239,4 @@ void soc_route_sci(uint8_t event);
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void enable_smi_generation(void);
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#endif
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#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */
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#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */
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@ -14,8 +14,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __STONEYRIDGE_H__
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#define __STONEYRIDGE_H__
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#ifndef __PICASSO_SB_H__
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#define __PICASSO_SB_H__
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#include <types.h>
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#include <device/device.h>
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@ -412,4 +412,4 @@ void i2c_soc_early_init(void);
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/* Initialize all the i2c buses that are not marked with early init. */
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void i2c_soc_init(void);
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#endif /* __STONEYRIDGE_H__ */
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#endif /* __PICASSO_SB_H__ */
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