exynos5420: add CPLL and DPLL to the known list of PLLs

This patch adds CPLL and DPLL to the known list of PLLs.

This is ported from https://gerrit.chromium.org/gerrit/#/c/62617/

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I2f2614e44cd9c98d98b8db9347f29de21703d1af
Reviewed-on: https://gerrit.chromium.org/gerrit/65282
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4461
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

src/cpu/samsung/exynos5420/clk.h

@@ -33,6 +33,8 @@ enum periph_id;
 #define BPLL	5
 #define RPLL	6
 #define SPLL	7
+#define CPLL	8
+#define DPLL	9
 
 enum pll_src_bit {
 	EXYNOS_SRC_CPLL = 1,

src/cpu/samsung/exynos5420/clock.c

@@ -103,6 +103,12 @@ unsigned long get_pll_clk(int pllreg)
 	case SPLL:
 		r = readl(&clk->spll_con0);
 		break;
+	case CPLL:
+		r = readl(&clk->cpll_con0);
+		break;
+	case DPLL:
+		r = readl(&clk->dpll_con0);
+		break;
 	default:
 		printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg);
 		return 0;