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mb/intel/adlrvp: Enable Camera in ADL-M RVP 

1. Configure Power Enable, Reset and Clock GPIO for both camera
2. Use same ASL code as ADL-P RVP

Configure RST, PWR_EN and IMGCLKOUT signals for WFC and UFC

TEST=Build, Boot and Verify streaming in both Camera

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50265
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Varshit Pandya 2021-02-03 21:32:39 +05:30 committed by Patrick Georgi
parent b9239315ed
commit 5f74818d39
1 changed files with 14 additions and 2 deletions
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16
src/mainboard/intel/adlrvp/gpio_m.c
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@ -11,14 +11,14 @@ static const struct pad_config gpio_table[] = {
/* H6 : I2C1 SDA */
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
/* B16 : I2C5 SDA */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
/* H5 : I2C0 SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
/* H7 : I2C1 SCL */
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
/* B17 : I2C5 SCL */
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
/* C5 : WWAN_PERST_N */
PAD_CFG_GPO(GPP_C5, 1, PLTRST),
@ -62,6 +62,18 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
/* CAM1_RST */
PAD_CFG_GPO(GPP_R5, 1, PLTRST),
/* CAM2_RST */
PAD_CFG_GPO(GPP_E15, 1, PLTRST),
/* CAM1_PWR_EN */
PAD_CFG_GPO(GPP_B23, 1, PLTRST),
/* CAM2_PWR_EN */
PAD_CFG_GPO(GPP_E16, 1, PLTRST),
/* IMGCLKOUT0 */
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
/* IMGCLKOUT1 */
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
};
void variant_configure_gpio_pads(void)