pciexp_device: Fix offset handling for extended capabilities
The PCIe spec explicitly states that the bottom-two bits of the next offset are reserved for future use and should be masked. We can also change the loop condition to avoid wrong offsets below 0x100 (exten- ded capabilities always reside in the extended config space). The whole patch series was tested on Google Samus and keeps the L1ss configuration of the WiFi device in tact. Change-Id: I0b622a0ce0a4a1127d266226ade0ec1e66e9fb79 Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66459 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -16,7 +16,7 @@ static unsigned int ext_cap_id(unsigned int cap)
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static unsigned int ext_cap_next_offset(unsigned int cap)
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{
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return cap >> 20;
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return cap >> 20 & 0xffc;
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}
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static unsigned int find_ext_cap_offset(const struct device *dev, unsigned int cap_id,
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@ -24,7 +24,7 @@ static unsigned int find_ext_cap_offset(const struct device *dev, unsigned int c
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{
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unsigned int this_cap_offset = offset;
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while (this_cap_offset != 0) {
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while (this_cap_offset >= PCIE_EXT_CAP_OFFSET) {
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const unsigned int this_cap = pci_read_config32(dev, this_cap_offset);
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/* Bail out when this request is unsupported */
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