siemens/mc_apl4: Clean up ramstage
Currently, there is nothing for this mainboard to do in ramstage. Change-Id: Id74a5f3f0a0583dc6bc81044913b8bb83d3b0b93 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer
Werner Zeh
parent
6c52c0b2ac
commit
5f82433206
3 changed files with 0 additions and 104 deletions
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@ -4,10 +4,6 @@ if BOARD_SIEMENS_MC_APL4
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config BOARD_SIEMENS_MC_APL4_VAR
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config BOARD_SIEMENS_MC_APL4_VAR
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def_bool y
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def_bool y
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select DRIVER_INTEL_I210
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select DRIVER_INTEL_I210
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select DRIVERS_I2C_RX6110SA
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select DRIVER_SIEMENS_NC_FPGA
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select NC_FPGA_NOTIFY_CB_READY
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select APL_SKIP_SET_POWER_LIMITS
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config DEVICETREE
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config DEVICETREE
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string
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string
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@ -1,3 +1 @@
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romstage-y += memory.c
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romstage-y += memory.c
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ramstage-y += mainboard.c
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@ -1,98 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Siemens AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootstate.h>
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#include <console/console.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <gpio.h>
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#include <hwilib.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/pcr_ids.h>
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#include <timer.h>
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#include <timestamp.h>
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#include <baseboard/variants.h>
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#define TX_DWORD3 0xa8c
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void variant_mainboard_final(void)
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{
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struct device *dev = NULL;
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/*
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* PIR6 register mapping for PCIe root ports
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* INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#
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*/
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pcr_write16(PID_ITSS, 0x314c, 0x0321);
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/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
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dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0);
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if (dev)
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pci_write_config8(dev, 0xd8, 0x3e);
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/* Enable CLKRUN_EN for power gating LPC */
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lpc_enable_pci_clk_cntl();
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/*
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* Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2
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* offset 0x341D bit3 and bit0.
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* Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2
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* offset 0x341C bit [3:0].
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*/
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pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
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/*
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* Correct the SATA transmit signal via the High Speed I/O Transmit
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* Control Register 3.
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* Bit [23:16] set the output voltage swing for TX line.
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* The value 0x4a sets the swing level to 0.58 V.
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*/
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pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));
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}
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static void wait_for_legacy_dev(void *unused)
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{
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uint32_t legacy_delay, us_since_boot;
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struct stopwatch sw;
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/* Open main hwinfo block. */
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if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
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return;
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/* Get legacy delay parameter from hwinfo. */
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if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay,
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sizeof(legacy_delay)) != sizeof(legacy_delay))
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return;
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us_since_boot = get_us_since_boot();
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/* No need to wait if the time since boot is already long enough.*/
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if (us_since_boot > legacy_delay)
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return;
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stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000);
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printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...",
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legacy_delay - us_since_boot, legacy_delay);
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stopwatch_wait_until_expired(&sw);
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printk(BIOS_NOTICE, "done!\n");
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}
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static void finalize_boot(void *unused)
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{
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/* Set coreboot ready LED. */
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gpio_output(CNV_RGI_DT, 1);
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);
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