spike-riscv: Look for the CBFS in RAM
Change-Id: I98927a70adc45d9aca916bd985932b94287921de Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15285 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
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@ -33,7 +33,6 @@ bootblock-y += trap_util.S
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bootblock-y += trap_handler.c
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bootblock-y += virtual_memory.c
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bootblock-y += boot.c
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bootblock-y += rom_media.c
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bootblock-y += misc.c
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bootblock-y += \
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$(top)/src/lib/memchr.c \
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@ -60,7 +59,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
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romstage-y += boot.c
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romstage-y += stages.c
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romstage-y += rom_media.c
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romstage-y += misc.c
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romstage-y += \
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$(top)/src/lib/memchr.c \
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@ -90,7 +88,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
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ramstage-y =
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ramstage-y += trap_handler.c
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ramstage-y += virtual_memory.c
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ramstage-y += rom_media.c
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ramstage-y += stages.c
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ramstage-y += misc.c
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ramstage-y += boot.c
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@ -15,11 +15,14 @@
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bootblock-y += bootblock.c
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bootblock-y += uart.c
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bootblock-y += qemu_util.c
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bootblock-y += rom_media.c
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romstage-y += romstage.c
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romstage-y += qemu_util.c
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romstage-y += uart.c
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romstage-y += rom_media.c
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ramstage-y += uart.c
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ramstage-y += qemu_util.c
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ramstage-y += rom_media.c
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bootblock-y += memlayout.ld
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romstage-y += memlayout.ld
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@ -15,11 +15,14 @@
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bootblock-y += bootblock.c
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bootblock-y += uart.c
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bootblock-y += spike_util.c
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bootblock-y += rom_media.c
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romstage-y += romstage.c
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romstage-y += uart.c
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romstage-y += spike_util.c
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romstage-y += rom_media.c
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ramstage-y += uart.c
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ramstage-y += spike_util.c
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ramstage-y += rom_media.c
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bootblock-y += memlayout.ld
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romstage-y += memlayout.ld
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@ -0,0 +1,30 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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* Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boot_device.h>
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/*
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* 0x80000000 is this start of RAM. We currently need to load coreboot.rom into
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* RAM on SPIKE, because SPIKE doesn't support loading custom code into the
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* boot ROM.
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*/
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static const struct mem_region_device boot_dev =
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MEM_REGION_DEV_RO_INIT(0x80000000, CONFIG_ROM_SIZE);
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const struct region_device *boot_device_ro(void)
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{
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return &boot_dev.rdev;
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}
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